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| author | Tom Rini <trini@konsulko.com> | 2016-09-30 21:58:44 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-09-30 21:58:44 -0400 |
| commit | fe4ba689a0cb2bb2ceafb88556a57bd80814b648 (patch) | |
| tree | 1012656ba1d3e9f8288d69de33c71417b2f22466 /drivers/usb/host/xhci-fsl.c | |
| parent | f413d1cae89143ad45b066b3d3bc602deafcb50a (diff) | |
| parent | 4c043712e9910ef1d612aedbd8304a1f7348ef5f (diff) | |
| download | u-boot-imx-fe4ba689a0cb2bb2ceafb88556a57bd80814b648.zip u-boot-imx-fe4ba689a0cb2bb2ceafb88556a57bd80814b648.tar.gz u-boot-imx-fe4ba689a0cb2bb2ceafb88556a57bd80814b648.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-usb
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
include/configs/dra7xx_evm.h
Diffstat (limited to 'drivers/usb/host/xhci-fsl.c')
| -rw-r--r-- | drivers/usb/host/xhci-fsl.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index bda5b5f..798c358 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -58,6 +58,13 @@ static void fsl_apply_xhci_errata(void) } } +static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg) +{ + clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK, + USB3_ENABLE_BEAT_BURST); + setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT); +} + static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) { int ret = 0; @@ -74,6 +81,22 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); + /* Change beat burst and outstanding pipelined transfers requests */ + fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg); + + /* + * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not + * reliably support Rx Detect in P3 mode(P3 is the default + * setting). Therefore, some USB3.0 devices may not be detected + * reliably in Super Speed mode. So, USB controller to configure + * USB in P2 mode whenever the Receive Detect feature is required. + * whenever the Receive Detect feature is required. + */ + if (has_erratum_a010151()) + clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0], + DWC3_GUSB3PIPECTL_DISRXDETP3, + DWC3_GUSB3PIPECTL_DISRXDETP3); + return ret; } |