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| author | Chin Liang See <clsee@altera.com> | 2016-09-21 10:26:04 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-10-27 08:03:12 +0200 |
| commit | bdef7876adf74dea6178f2143705bc41262c7b06 (patch) | |
| tree | bf7186c26acdd0e71077bd1ac68d338f9e3f3fdd /drivers/sysreset/sysreset-uclass.c | |
| parent | 13022d852d5c233894fabb62279a2ae9e0355638 (diff) | |
| download | u-boot-imx-bdef7876adf74dea6178f2143705bc41262c7b06.zip u-boot-imx-bdef7876adf74dea6178f2143705bc41262c7b06.tar.gz u-boot-imx-bdef7876adf74dea6178f2143705bc41262c7b06.tar.bz2 | |
arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'drivers/sysreset/sysreset-uclass.c')
0 files changed, 0 insertions, 0 deletions