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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-08-10 08:51:50 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:25 +0200
commitcd2004037c01be34ebd61f49755fd252d03131aa (patch)
treeacbb26cfa8437894fba7a03ced61ef8dea2b6a92 /drivers/spi
parent78befb695d0b28d9888fe5dee27dc80b24eac1c9 (diff)
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mxc_spi: Round up clock divider
Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/mxc_spi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2e15318..cf1462f 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -96,7 +96,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
clk_src = mxc_get_clock(MXC_CSPI_CLK);
- div = clk_src / max_hz;
+ div = DIV_ROUND_UP(clk_src, max_hz);
div = get_cspi_div(div);
debug("clk %d Hz, div %d, real clk %d Hz\n",
@@ -147,7 +147,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
* The following computation is taken directly from Freescale's code.
*/
if (clk_src > max_hz) {
- pre_div = clk_src / max_hz;
+ pre_div = DIV_ROUND_UP(clk_src, max_hz);
if (pre_div > 16) {
post_div = pre_div / 16;
pre_div = 15;