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| author | Tom Rini <trini@ti.com> | 2013-04-15 07:46:11 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-04-15 07:46:11 -0400 |
| commit | 17059f972fa6768ebf15a575c00083b3a431b79a (patch) | |
| tree | 30df6b88fa1dc57dada54f9a16ab1619cc4f3c52 /drivers/spi | |
| parent | 277f037074fbb73be10a7bff27079b6eb0a3bfbb (diff) | |
| parent | 8960af8ba9488fc54e2e4733cbada26d3cece225 (diff) | |
| download | u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.zip u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.tar.gz u-boot-imx-17059f972fa6768ebf15a575c00083b3a431b79a.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/exynos_spi.c | 2 | ||||
| -rw-r--r-- | drivers/spi/mxc_spi.c | 17 |
2 files changed, 11 insertions, 8 deletions
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 51b3d30..607e1cd 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -358,6 +358,7 @@ static inline struct exynos_spi *get_spi_base(int dev_index) * @param bus SPI bus structure to fill with information * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing */ +#ifdef CONFIG_OF_CONTROL static int spi_get_config(const void *blob, int node, struct spi_bus *bus) { bus->node = node; @@ -413,6 +414,7 @@ static int process_nodes(const void *blob, int node_list[], int count) return 0; } +#endif /* Sadly there is no error return from this function */ void spi_init(void) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index d792d8d..5bed858 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, return -1; } - reg_ctrl = reg_read(®s->ctrl); - - /* Reset spi */ - reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN)); - reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN)); + /* + * Reset SPI and set all CSs to master mode, if toggling + * between slave and master mode we might see a glitch + * on the clock line + */ + reg_ctrl = MXC_CSPICTRL_MODE_MASK; + reg_write(®s->ctrl, reg_ctrl); + reg_ctrl |= MXC_CSPICTRL_EN; + reg_write(®s->ctrl, reg_ctrl); /* * The following computation is taken directly from Freescale's code. @@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | MXC_CSPICTRL_POSTDIV(post_div); - /* always set to master mode */ - reg_ctrl |= 1 << (cs + 4); - /* We need to disable SPI before changing registers */ reg_ctrl &= ~MXC_CSPICTRL_EN; |