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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-04-14 10:38:37 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-04-14 10:38:37 +0200
commit8dc16cf9dd6196d99969d12741df186a61a2f9a3 (patch)
tree9a708a8fc9cfaa2cedbcb60900d72c3807b3e522 /drivers/spi/mxc_spi.c
parentf84a7b8f54db51172a50926be8b2224413977f75 (diff)
parent0f1411bc8dade4472ca802f46f75714e67301bb0 (diff)
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'drivers/spi/mxc_spi.c')
-rw-r--r--drivers/spi/mxc_spi.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index cb48019..5bed858 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
return -1;
}
- /* Reset spi */
- reg_write(&regs->ctrl, 0);
- reg_write(&regs->ctrl, MXC_CSPICTRL_EN);
-
- reg_ctrl = reg_read(&regs->ctrl);
+ /*
+ * Reset SPI and set all CSs to master mode, if toggling
+ * between slave and master mode we might see a glitch
+ * on the clock line
+ */
+ reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+ reg_write(&regs->ctrl, reg_ctrl);
+ reg_ctrl |= MXC_CSPICTRL_EN;
+ reg_write(&regs->ctrl, reg_ctrl);
/*
* The following computation is taken directly from Freescale's code.
@@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* always set to master mode */
- reg_ctrl |= 1 << (cs + 4);
-
/* We need to disable SPI before changing registers */
reg_ctrl &= ~MXC_CSPICTRL_EN;