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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-24 22:32:44 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-04-01 00:54:00 +0900 |
commit | 8cc92b996ddecd4c364d0bbb474c3569ebec55c7 (patch) | |
tree | 6a726da2b75e7e8f4a495519c19fde6a6c3ecdbb /drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | |
parent | 510454db045143e374a7d64e6bb043799d0023d7 (diff) | |
download | u-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.zip u-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.tar.gz u-boot-imx-8cc92b996ddecd4c364d0bbb474c3569ebec55c7.tar.bz2 |
pinctrl: uniphier: introduce capability flag
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens
because pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones. Having flags would be better than
adding new members every time a new SoC-specific capability comes up.
At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier-core.c')
-rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index ac3a06c..bb7a088 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -68,14 +68,33 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, unsigned muxval) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); - unsigned mux_bits = priv->socdata->mux_bits; - unsigned reg_stride = priv->socdata->reg_stride; - unsigned reg, reg_end, shift, mask; + unsigned mux_bits, reg_stride, reg, reg_end, shift, mask; + bool load_pinctrl; u32 tmp; /* some pins need input-enabling */ uniphier_pinconf_input_enable(dev, pin); + if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { + /* + * Mode offset bit + * Normal 4 * n shift+3:shift + * Debug 4 * n shift+7:shift+4 + */ + mux_bits = 4; + reg_stride = 8; + load_pinctrl = true; + } else { + /* + * Mode offset bit + * Normal 8 * n shift+3:shift + * Debug 8 * n + 4 shift+3:shift + */ + mux_bits = 8; + reg_stride = 4; + load_pinctrl = false; + } + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -94,7 +113,7 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, muxval >>= mux_bits; } - if (priv->socdata->load_pinctrl) + if (load_pinctrl) writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); } |