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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-10-02 14:53:27 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-10-02 14:53:27 +0200
commitf04c53762962280365005c9db12ab561a18f2692 (patch)
tree6cd2fa04929473afda1cceaa297cd340792bd326 /drivers/net
parent5c8d5b6fc15fc2c52d74c266d9fe6eb5f75cbcb4 (diff)
parentce7a7f5e6bda35d7d0972be07b6983552d1a2cb2 (diff)
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/fec_mxc.c4
-rw-r--r--drivers/net/fec_mxc.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 690e572..107cd6e 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -453,7 +453,7 @@ static int fec_open(struct eth_device *edev)
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
/*
* setup the MII gasket for RMII mode
@@ -794,7 +794,7 @@ static int fec_recv(struct eth_device *dev)
uint16_t bd_status;
uint32_t addr, size, end;
int i;
- uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
/*
* Check if any critical events have happened
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 4b4f8b7..0717cc6 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -135,7 +135,7 @@ struct ethernet_regs {
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
@@ -202,7 +202,7 @@ struct ethernet_regs {
#define FEC_X_DES_ACTIVE_TDAR 0x01000000
#define FEC_R_DES_ACTIVE_RDAR 0x01000000
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
/* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6)