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authorRuchika Gupta <ruchika.gupta@freescale.com>2012-04-19 02:27:11 +0000
committerJoe Hershberger <joe.hershberger@ni.com>2012-12-15 12:28:21 -0600
commit776e66e8f1df7f092e6a543d47391a85509c1a2b (patch)
treeaac0b4fbc3069b855a4847674213ab5478cea7cc /drivers/net
parentebbf0d20aa85f623c49b7ed3349ebfea450c152d (diff)
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e1000e : Correct Rx Threshold granularity
In e1000e driver, Rx descriptor queue is used such that hardware can add only one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set to single descriptor. This would ensure that every time controller fills a Rx descriptor, it is flushed to host memory. Earlier this granularity was in cache line units i.e 2 descriptors. This leads to controller always waiting for 2 descriptors before flushing them out. But since not more than one Rx BD is actually available , the accumulation condition never gets hit. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/e1000.c10
-rw-r--r--drivers/net/e1000.h1
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 2d4da4b..8ba98b2 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1688,6 +1688,16 @@ e1000_init_hw(struct eth_device *nic)
E1000_WRITE_REG(hw, TXDCTL, ctrl);
}
+ /* Set the receive descriptor write back policy */
+
+ if (hw->mac_type >= e1000_82571) {
+ ctrl = E1000_READ_REG(hw, RXDCTL);
+ ctrl =
+ (ctrl & ~E1000_RXDCTL_WTHRESH) |
+ E1000_RXDCTL_FULL_RX_DESC_WB;
+ E1000_WRITE_REG(hw, RXDCTL, ctrl);
+ }
+
switch (hw->mac_type) {
default:
break;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index fd1d8f8..1bbae50 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1551,6 +1551,7 @@ struct e1000_hw {
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
/* Transmit Descriptor Control */
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */