drivers/mc: Migrated MC Flibs to 0.5.2

Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

5 files changed, 523 insertions, 0 deletions

diff --git a/drivers/net/fsl-mc/Makefile b/drivers/net/fsl-mc/Makefile
new file mode 100644
index 0000000..206ac6b
--- /dev/null
+++ b/drivers/net/fsl-mc/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Layerscape MC driver
+obj-y += mc.o \
+	mc_sys.o \
+	dpmng.o
diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c
new file mode 100644
index 0000000..cc14c7b
--- /dev/null
+++ b/drivers/net/fsl-mc/dpmng.c
@@ -0,0 +1,91 @@
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmng.h>
+#include "fsl_dpmng_cmd.h"
+
+int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
+					  MC_CMD_PRI_LOW, 0);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
+
+	return 0;
+}
+
+int dpmng_reset_aiop(struct fsl_mc_io *mc_io, int container_id,
+		     int aiop_tile_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_AIOP,
+					  MC_CMD_PRI_LOW, 0);
+	DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_load_aiop(struct fsl_mc_io *mc_io,
+		    int container_id,
+		    int aiop_tile_id,
+		    uint64_t img_iova,
+		    uint32_t img_size)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_LOAD_AIOP,
+					  MC_CMD_PRI_LOW,
+					  0);
+	DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size,
+			    img_iova);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_run_aiop(struct fsl_mc_io *mc_io,
+		   int container_id,
+		   int aiop_tile_id,
+		   const struct dpmng_aiop_run_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RUN_AIOP,
+					  MC_CMD_PRI_LOW,
+					  0);
+	DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_MC_PORTAL,
+					  MC_CMD_PRI_LOW,
+					  0);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
new file mode 100644
index 0000000..c9fe021
--- /dev/null
+++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
@@ -0,0 +1,49 @@
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __FSL_DPMNG_CMD_H
+#define __FSL_DPMNG_CMD_H
+
+/* Command IDs */
+#define DPMNG_CMDID_GET_VERSION			0x831
+#define DPMNG_CMDID_RESET_AIOP			0x832
+#define DPMNG_CMDID_LOAD_AIOP			0x833
+#define DPMNG_CMDID_RUN_AIOP			0x834
+#define DPMNG_CMDID_RESET_MC_PORTAL		0x835
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, uint32_t, mc_ver_info->revision); \
+	MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, mc_ver_info->minor); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \
+			    img_iova) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, img_size); \
+	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, img_iova); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->cores_mask); \
+	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, cfg->options); \
+} while (0)
+
+#endif /* __FSL_DPMNG_CMD_H */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
new file mode 100644
index 0000000..74b0085
--- /dev/null
+++ b/drivers/net/fsl-mc/mc.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <errno.h>
+#include <asm/io.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_dpmng.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+static int mc_boot_status;
+
+/**
+ * Copying MC firmware or DPL image to DDR
+ */
+static int mc_copy_image(const char *title,
+			 u64 image_addr, u32 image_size, u64 mc_ram_addr)
+{
+	debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
+	memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+	return 0;
+}
+
+/**
+ * MC firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates
+ * raw image address and size values.
+ * Returns 0 on success and a negative errno on error.
+ * task fail.
+ **/
+int parse_mc_firmware_fit_image(const void **raw_image_addr,
+				size_t *raw_image_size)
+{
+	int format;
+	void *fit_hdr;
+	int node_offset;
+	const void *data;
+	size_t size;
+	const char *uname = "firmware";
+
+	/* Check if the image is in NOR flash */
+#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
+	fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
+#endif
+
+	/* Check if Image is in FIT format */
+	format = genimg_get_format(fit_hdr);
+
+	if (format != IMAGE_FORMAT_FIT) {
+		printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
+		return -EINVAL;
+	}
+
+	if (!fit_check_format(fit_hdr)) {
+		printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
+		return -EINVAL;
+	}
+
+	node_offset = fit_image_get_node(fit_hdr, uname);
+
+	if (node_offset < 0) {
+		printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
+		return -ENOENT;
+	}
+
+	/* Verify MC firmware image */
+	if (!(fit_image_verify(fit_hdr, node_offset))) {
+		printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
+	}
+
+	/* Get address and size of raw image */
+	fit_image_get_data(fit_hdr, node_offset, &data, &size);
+
+	*raw_image_addr = data;
+	*raw_image_size = size;
+
+	return 0;
+}
+
+int mc_init(bd_t *bis)
+{
+	int error = 0;
+	int timeout = 200000;
+	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+	u64 mc_ram_addr;
+	u64 mc_dpl_offset;
+	u32 reg_gsr;
+	u32 mc_fw_boot_status;
+	void *dpl_fdt_hdr;
+	int dpl_size;
+	const void *raw_image_addr;
+	size_t raw_image_size = 0;
+	struct fsl_mc_io mc_io;
+	int portal_id;
+	struct mc_version mc_ver_info;
+
+	/*
+	 * The MC private DRAM block was already carved at the end of DRAM
+	 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
+	 */
+	if (gd->bd->bi_dram[1].start) {
+		mc_ram_addr =
+			gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+	} else {
+		mc_ram_addr =
+			gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+	}
+
+	/*
+	 * Management Complex cores should be held at reset out of POR.
+	 * U-boot should be the first software to touch MC. To be safe,
+	 * we reset all cores again by setting GCR1 to 0. It doesn't do
+	 * anything if they are held at reset. After we setup the firmware
+	 * we kick off MC by deasserting the reset bit for core 0, and
+	 * deasserting the reset bits for Command Portal Managers.
+	 * The stop bits are not touched here. They are used to stop the
+	 * cores when they are active. Setting stop bits doesn't stop the
+	 * cores from fetching instructions when they are released from
+	 * reset.
+	 */
+	out_le32(&mc_ccsr_regs->reg_gcr1, 0);
+	dmb();
+
+	error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
+	if (error != 0)
+		goto out;
+	/*
+	 * Load the MC FW at the beginning of the MC private DRAM block:
+	 */
+	mc_copy_image("MC Firmware",
+		      (u64)raw_image_addr, raw_image_size, mc_ram_addr);
+
+	/*
+	 * Get address and size of the DPL blob stored in flash:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
+	dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
+#endif
+
+	error = fdt_check_header(dpl_fdt_hdr);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
+		goto out;
+	}
+
+	dpl_size = fdt_totalsize(dpl_fdt_hdr);
+	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+		printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
+		       dpl_size);
+		error = -EINVAL;
+		goto out;
+	}
+
+	/*
+	 * Calculate offset in the MC private DRAM block at which the MC DPL
+	 * blob is to be placed:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+
+	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+#else
+	mc_dpl_offset = mc_get_dram_block_size() -
+			roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096);
+
+	if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
+		printf("%s: Invalid MC DPL offset: %llu\n",
+		       __func__, mc_dpl_offset);
+		error = -EINVAL;
+		goto out;
+	}
+#endif
+
+	/*
+	 * Load the MC DPL blob at the far end of the MC private DRAM block:
+	 *
+	 * TODO: Should we place the DPL at a different location to match
+	 * assumptions of MC firmware about its memory layout?
+	 */
+	mc_copy_image("MC DPL blob",
+		      (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
+
+	debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+
+	/*
+	 * Tell MC where the MC Firmware image was loaded in DDR:
+	 */
+	out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
+	out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
+	out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
+
+	/*
+	 * Tell MC where the DPL blob was loaded in DDR, by indicating
+	 * its offset relative to the beginning of the DDR block
+	 * allocated to the MC firmware. The MC firmware is responsible
+	 * for checking that there is no overlap between the DPL blob
+	 * and the runtime heap and stack of the MC firmware itself.
+	 *
+	 * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
+	 * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
+	 * aligned.
+	 * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
+	 * this case as the SoC COP or PIC will be signaled.
+	 */
+	out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
+
+	printf("\nfsl-mc: Booting Management Complex ...\n");
+
+	/*
+	 * Deassert reset and release MC core 0 to run
+	 */
+	out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
+	dmb();
+	debug("Polling mc_ccsr_regs->reg_gsr ...\n");
+
+	for (;;) {
+		reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
+		mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
+		if (mc_fw_boot_status & 0x1)
+			break;
+
+		udelay(1000);	/* throttle polling */
+		if (timeout-- <= 0)
+			break;
+	}
+
+	if (timeout <= 0) {
+		printf("fsl-mc: timeout booting management complex firmware\n");
+
+		/* TODO: Get an error status from an MC CCSR register */
+		error = -ETIMEDOUT;
+		goto out;
+	}
+
+	if (mc_fw_boot_status != 0x1) {
+		/*
+		 * TODO: Identify critical errors from the GSR register's FS
+		 * field and for those errors, set error to -ENODEV or other
+		 * appropriate errno, so that the status property is set to
+		 * failure in the fsl,dprc device tree node.
+		 */
+		printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
+		       reg_gsr);
+	}
+
+	/*
+	 * TODO: need to obtain the portal_id for the root container from the
+	 * DPL
+	 */
+	portal_id = 0;
+
+	/*
+	 * Check that the MC firmware is responding portal commands:
+	 */
+	mc_io.mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+	debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
+	      portal_id, mc_io.mmio_regs);
+
+	error = mc_get_version(&mc_io, &mc_ver_info);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
+		       error);
+		goto out;
+	}
+
+	if (MC_VER_MAJOR != mc_ver_info.major)
+		printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
+		       mc_ver_info.major, MC_VER_MAJOR);
+
+	if (MC_VER_MINOR != mc_ver_info.minor)
+		printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
+		       mc_ver_info.minor, MC_VER_MINOR);
+
+	printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
+	       mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
+	       mc_fw_boot_status);
+out:
+	if (error != 0)
+		mc_boot_status = -error;
+	else
+		mc_boot_status = 0;
+
+	return error;
+}
+
+int get_mc_boot_status(void)
+{
+	return mc_boot_status;
+}
+
+/**
+ * Return the actual size of the MC private DRAM block.
+ *
+ * NOTE: For now this function always returns the minimum required size,
+ * However, in the future, the actual size may be obtained from an environment
+ * variable.
+ */
+unsigned long mc_get_dram_block_size(void)
+{
+	return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+}
diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c
new file mode 100644
index 0000000..7c8e003
--- /dev/null
+++ b/drivers/net/fsl-mc/mc_sys.c
@@ -0,0 +1,63 @@
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Author: German Rivera <German.Rivera@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define MC_CMD_HDR_READ_CMDID(_hdr) \
+	((uint16_t)u64_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S))
+
+/**
+ * mc_send_command - Send MC command and wait for response
+ *
+ * @mc_io: Pointer to MC I/O object to be used
+ * @cmd: MC command buffer. On input, it contains the command to send to the MC.
+ * On output, it contains the response from the MC if any.
+ *
+ * Depending on the sharing option specified when creating the MC portal
+ * wrapper, this function will use a spinlock or mutex to ensure exclusive
+ * access to the MC portal from the point when the command is sent until a
+ * response is received from the MC.
+ */
+int mc_send_command(struct fsl_mc_io *mc_io,
+		    struct mc_command *cmd)
+{
+	enum mc_cmd_status status;
+	int timeout = 2000;
+
+	mc_write_command(mc_io->mmio_regs, cmd);
+
+	for ( ; ; ) {
+		status = mc_read_response(mc_io->mmio_regs, cmd);
+		if (status != MC_CMD_STATUS_READY)
+			break;
+
+		if (--timeout == 0) {
+			printf("Error: Timeout waiting for MC response\n");
+			return -ETIMEDOUT;
+		}
+
+		udelay(500);
+	}
+
+	if (status != MC_CMD_STATUS_OK) {
+		printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
+		       mc_io->mmio_regs,
+		       (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header),
+		       (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
+		       (unsigned int)status);
+
+		return -EIO;
+	}
+
+	return 0;
+}