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authorStefano Babic <sbabic@denx.de>2014-08-11 10:21:03 +0200
committerStefano Babic <sbabic@denx.de>2014-08-11 10:21:03 +0200
commite82abaeb7f2a0833fccf90460c48b9f2100258f8 (patch)
treede701f5c90b7373966412d566b5c00d3837954bc /drivers/mtd
parentf93f21906e374d46c6abfbdf4eb9cb1ab51b6384 (diff)
parent1899fac925eda817e12234aef3d01d354788662e (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c45
-rw-r--r--drivers/mtd/nand/fsl_ifc_spl.c6
-rw-r--r--drivers/mtd/spi/sf_ops.c1
3 files changed, 45 insertions, 7 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index be5a16a..8b453cb 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -19,8 +19,11 @@
#include <asm/errno.h>
#include <fsl_ifc.h>
-#define FSL_IFC_V1_1_0 0x01010000
-#define MAX_BANKS 4
+#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#endif
+
+#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
#define ERR_BYTE 0xFF /* Value returned for read bytes
when read failed */
#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
@@ -802,12 +805,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
{
}
-static void fsl_ifc_sram_init(void)
+static int fsl_ifc_sram_init(uint32_t ver)
{
struct fsl_ifc *ifc = ifc_ctrl->regs;
uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
+ uint32_t ncfgr = 0;
long long end_tick;
+ if (ver > FSL_IFC_V1_1_0) {
+ ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
+ ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
+
+ /* wait for SRAM_INIT bit to be clear or timeout */
+ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+ while (end_tick > get_ticks()) {
+ ifc_ctrl->status =
+ ifc_in32(&ifc->ifc_nand.nand_evter_stat);
+
+ if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
+ return 0;
+ }
+ printf("fsl-ifc: Failed to Initialise SRAM\n");
+ return 1;
+ }
+
cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
/* Save CSOR and CSOR_ext */
@@ -850,11 +871,18 @@ static void fsl_ifc_sram_init(void)
break;
}
+ if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
+ printf("fsl-ifc: Failed to Initialise SRAM\n");
+ return 1;
+ }
+
ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
/* Restore CSOR and CSOR_ext */
ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+
+ return 0;
}
static int fsl_ifc_chip_init(int devnum, u8 *addr)
@@ -864,7 +892,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
struct fsl_ifc_mtd *priv;
struct nand_ecclayout *layout;
uint32_t cspr = 0, csor = 0, ver = 0;
- int ret;
+ int ret = 0;
if (!ifc_ctrl) {
fsl_ifc_ctrl_init();
@@ -1006,8 +1034,13 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
}
ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
- if (ver == FSL_IFC_V1_1_0)
- fsl_ifc_sram_init();
+ if (ver >= FSL_IFC_V1_1_0)
+ ret = fsl_ifc_sram_init(ver);
+ if (ret)
+ return ret;
+
+ if (ver >= FSL_IFC_V2_0_0)
+ priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
ret = nand_scan_ident(mtd, 1, NULL);
if (ret)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 5100772..e336cb1 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
int pages_per_blk;
int blk_size;
int bad_marker = 0;
- int bufnum_mask, bufnum;
+ int bufnum_mask, bufnum, ver = 0;
int csor, cspr;
int pos = 0;
@@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
bad_marker = 5;
}
+ ver = ifc_in32(&ifc->ifc_rev);
+ if (ver >= FSL_IFC_V2_0_0)
+ bufnum_mask = (bufnum_mask * 2) + 1;
+
pages_per_blk =
32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index ef91b92..85cf22d 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -421,6 +421,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
data += read_len;
}
+ free(cmd);
return ret;
}