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authorRostislav Lisovy <lisovy@gmail.com>2014-09-09 15:54:30 +0200
committerScott Wood <scottwood@freescale.com>2014-09-25 13:43:00 -0500
commit2f665945b39a9972260cbcf60d5e7f2a60587f5e (patch)
tree42d1615242c1f74862e56a66f6137697c32ef39c /drivers/mtd
parente3a4facdfc07179ebe017a07b8de6224a935a9f3 (diff)
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mtd: nand: am335x: Fix 'bit-flip' errors in SPL
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html The issue was partially fixed with the cc81a5291910d7a.git however this has to be done to fix the SPL. The original author of the code is Belisko Marek <marek.belisko@gmail.com> Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/am335x_spl_bch.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index ce65d8e..bf8b2ee 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -64,14 +64,18 @@ static int nand_command(int block, int page, uint32_t offs,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+ if (cmd != NAND_CMD_RNDOUT) {
+ hwctrl(&nand_info[0], (page_addr & 0xff),
+ NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices > 128MiB */
- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+ /* One more address cycle for devices > 128MiB */
+ hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
+ }
+
hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {