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authorHaijun.Zhang <Haijun.Zhang@freescale.com>2014-03-18 17:04:23 +0800
committerPantelis Antoniou <panto@antoniou-consulting.com>2014-04-02 13:25:01 +0300
commit1336e2d343f088b71ec71907855caccd1053d166 (patch)
tree505f786336b504d77007f0076c310a0ec0a5942c /drivers/mmc
parent8a573022c38da9ecc749acbc60556a8e8bd41996 (diff)
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mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/fsl_esdhc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 00a454f..4c3b93d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
timeout++;
#endif
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+ timeout = 0xE;
+#endif
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;