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authorOtavio Salvador <otavio@ossystems.com.br>2013-01-22 15:01:02 +0000
committerStefano Babic <sbabic@denx.de>2013-01-28 11:43:01 +0100
commit8000d8a8260c95727b6357a638a5e80625d7a899 (patch)
tree3b1e8902aacb992854decd229a264df125647b41 /drivers/mmc/mxsmmc.c
parentf3801e2b9bd5b86b5d43d10795ebc56cf4d785fa (diff)
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mxs: mmc: Fix MMC reset on iMX23
This does the same reset mask as done in v3.7 Linux kernel code. The block is properly configured for MMC operation that way. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/mmc/mxsmmc.c')
-rw-r--r--drivers/mmc/mxsmmc.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 0c4cd54..9d71202 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -334,11 +334,17 @@ static int mxsmmc_init(struct mmc *mmc)
/* Reset SSP */
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
- /* 8 bits word length in MMC mode */
- clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
- SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
- SSP_CTRL1_DMA_ENABLE,
- SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
+ /* Reconfigure the SSP block for MMC operation */
+ writel(SSP_CTRL1_SSP_MODE_SD_MMC |
+ SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
+ SSP_CTRL1_DMA_ENABLE |
+ SSP_CTRL1_POLARITY |
+ SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+ SSP_CTRL1_DATA_CRC_IRQ_EN |
+ SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+ SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+ SSP_CTRL1_RESP_ERR_IRQ_EN,
+ &ssp_regs->hw_ssp_ctrl1_set);
/* Set initial bit clock 400 KHz */
mxs_set_ssp_busclock(priv->id, 400);