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| author | Ye.Li <B37916@freescale.com> | 2015-12-14 17:07:46 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2015-12-14 17:23:27 +0800 |
| commit | f355f117a6d735b0c3cba79f1cb24829cf8cae25 (patch) | |
| tree | bb7444d31873d55e03cc0fae7b8dc1015fb3a7a3 /drivers/mmc/fsl_esdhc.c | |
| parent | ec3be63af97ed6a301adb6bf8daf2781a9442812 (diff) | |
| download | u-boot-imx-f355f117a6d735b0c3cba79f1cb24829cf8cae25.zip u-boot-imx-f355f117a6d735b0c3cba79f1cb24829cf8cae25.tar.gz u-boot-imx-f355f117a6d735b0c3cba79f1cb24829cf8cae25.tar.bz2 | |
MLK-12001 MMC:USDHC: Clear DLL_CTRL delay line settings at driver init
Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the
pre-settings from boot rom. U-boot should re-init the USDHC not reply on the
value set by boot from.
On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021,
when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors.
Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6356bc5..7d002b5 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -530,6 +530,9 @@ static int esdhc_init(struct mmc *mmc) /* Put VEND_SPEC to default value */ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); + + /* Disable DLL_CTRL delay line */ + esdhc_write32(®s->dllctrl, 0x0); #endif #ifndef ARCH_MXC |