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author | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:15:19 +0200 |
commit | 87a5d601031652293ec4b729fdb7ee01bbd940a8 (patch) | |
tree | 91ede3ee45b228736c1876a700024782d7bc2032 /drivers/dma/omap3_dma.c | |
parent | 606a76f8ef479e42ae4d06f8f3ce87e9a1c72acf (diff) | |
parent | 37fc0ed268dc5acacd3a83adafa26eb1a84e90af (diff) | |
download | u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.zip u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.gz u-boot-imx-87a5d601031652293ec4b729fdb7ee01bbd940a8.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
ARM: Add Calxeda Highbank platform
dkb: make mmc command as default enabled
Marvell: dkb: add mmc support
ARM: pantheon: add mmc definition
davinci: remove config.mk file from the sources
ARM:AM33XX: Add support for TI AM335X EVM
ARM:AM33XX: Added timer support
ARM:AM33XX: Add emif/ddr support
ARM:AM33XX: Add clock definitions
ARM:AM33XX: Added support for AM33xx
omap3/emif4: fix registers definition
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
davinci: emac: add support for more than 1 PHYs
davinci: emac: add new features to autonegotiate for EMAC
da850evm: Move LPSC configuration to board_early_init_f()
omap4_panda: Build in cmd_gpio support on panda
omap: Don't use gpio_free to change direction to input
mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
OMAP3: overo : Add environment variable optargs to bootargs
OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
OMAP3: overo : Use ttyO2 instead of ttyS2.
da830: add support for NAND boot mode
dm36x: revert cache disable patch
dm644X: revert cache disable patch
devkit8000: Add malloc space
omap: spl: fix build break due to changes in FAT
OMAP3 SPL: Provide weak omap_rev_string
omap: beagle: Use ubifs instead of jffs2 for nand boot
omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
omap: overo: Configure mux for gpio10
SPL: Add DMA library
omap3: Add interface for omap3 DMA
omap3: Add DMA register accessors
omap3: Add Base register for DMA
arm, davinci: add missing LSPC define for MMC/SD1
U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
DaVinci: correct MDSTAT.STATE mask
omap4: splitting padconfs into common, 4430 and 4460
omap4: adding revision detection for 4460 ES1.1
omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
gplug: fixed build error as a result of code cleanup patch
kirkwood_spi: add dummy spi_init()
gpio: mvmfp: reduce include platform file
ARM: orion5x: reduce dependence of including platform file
serial: reduce include platform file for marvell chip
ARM: kirkwood: reduce dependence of including platform file
ARM: armada100: reduce dependence of including platform file
ARM: pantheon: reduce dependence of including platform file
Armada100: Add env storage support for Marvell gplugD
Armada100: Add SPI flash support for Marvell gplugD
Armada100: Add SPI support for Marvell gplugD
SPI: Add SPI driver support for Marvell Armada100
dreamplug: initial board support.
imx: fix coding style
misc: pmic: drop old Freescale's pmic driver
MX31: mx31pdk: use new pmic driver
MX31: mx31ads: use new pmic driver
MX31: mx31_litekit: use new pmic driver
MX5: mx53evk: use new pmic driver
MX5: mx51evk: use new pmic driver
MX35: mx35pdk: use new pmic driver
misc: pmic: addI2C support to pmic_fsl driver
misc: pmic: use I2C_SET_BUS in pmic I2C
MX5: efikamx/efikasb: use new pmic driver
MX3: qong: use new pmic driver
RTC: Switch mc13783 to generic pmic code
MX5: vision2: use new pmic driver
misc: pmic: Freescale PMIC switches to generic PMIC driver
misc:pmic:samsung Enable PMIC driver at GONI target
misc:pmic:max8998 MAX8998 support at a new PMIC driver.
misc:pmic:core New generic PMIC driver
mx31pdk: Remove unneeded config
mx31: provide readable WEIM CS accessor
MX51: vision2: Set global macros
I2C: Add i2c_get/set_speed() to mxc_i2c.c
ARM: Update mach-types
devkit8000: Add config to enable SPL MMC boot
devkit8000: protect board_mmc_init
arm, post: add missing post_time_ms for arm
cosmetic, post: Codingstyle cleanup
arm, logbuffer: make it compileclean
tegra2: Enable MMC for Seaboard
tegra2: Add more pinmux functions
tegra2: Rename PIN_ to PINGRP_
tegra2: Add more clock functions
tegra2: Clean up board code a little
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Diffstat (limited to 'drivers/dma/omap3_dma.c')
-rw-r--r-- | drivers/dma/omap3_dma.c | 180 |
1 files changed, 180 insertions, 0 deletions
diff --git a/drivers/dma/omap3_dma.c b/drivers/dma/omap3_dma.c new file mode 100644 index 0000000..b98eca1 --- /dev/null +++ b/drivers/dma/omap3_dma.c @@ -0,0 +1,180 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3 + * Tested on Silicon Revision major:0x4 minor:0x0 + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/omap3.h> +#include <asm/arch/dma.h> +#include <asm/io.h> +#include <asm/errno.h> + +static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE; +uint32_t dma_active; /* if a transfer is started the respective + bit is set for the logical channel */ + +/* Check if we have the given channel + * PARAMETERS: + * chan: Channel number + * + * RETURN of non-zero means error */ +static inline int check_channel(uint32_t chan) +{ + if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX) + return -EINVAL; + return 0; +} + +static inline void reset_irq(uint32_t chan) +{ + /* reset IRQ reason */ + writel(0x1DFE, &dma4_cfg->chan[chan].csr); + /* reset IRQ */ + writel((1 << chan), &dma4_cfg->irqstatus_l[0]); + dma_active &= ~(1 << chan); +} + +/* Set Source, Destination and Size of DMA transfer for the + * specified channel. + * PARAMETERS: + * chan: channel to use + * src: source of the transfer + * dst: destination of the transfer + * sze: Size of the transfer + * + * RETURN of non-zero means error */ +int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, + uint32_t sze) +{ + if (check_channel(chan)) + return -EINVAL; + /* CDSA0 */ + writel((uint32_t)src, &dma4_cfg->chan[chan].cssa); + writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa); + writel(sze, &dma4_cfg->chan[chan].cen); +return 0; +} + +/* Start the DMA transfer */ +int omap3_dma_start_transfer(uint32_t chan) +{ + uint32_t val; + + if (check_channel(chan)) + return -EINVAL; + + val = readl(&dma4_cfg->chan[chan].ccr); + /* Test for channel already in use */ + if (val & CCR_ENABLE_ENABLE) + return -EBUSY; + + writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr); + dma_active |= (1 << chan); + debug("started transfer...\n"); + return 0; +} + +/* Busy-waiting for a DMA transfer + * This has to be called before another transfer is started + * PARAMETER + * chan: Channel to wait for + * + * RETURN of non-zero means error*/ +int omap3_dma_wait_for_transfer(uint32_t chan) +{ + uint32_t val; + + if (!(dma_active & (1 << chan))) { + val = readl(&dma4_cfg->irqstatus_l[0]); + if (!(val & chan)) { + debug("dma: The channel you are trying to wait for " + "was never activated - ERROR\n"); + return -1; /* channel was never active */ + } + } + + /* all irqs on line 0 */ + while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan))) + asm("nop"); + + val = readl(&dma4_cfg->chan[chan].csr); + if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) | + (val & CSR_MISALIGNED_ADRS_ERR)) { + debug("err code: %X\n", val); + debug("dma: transfer error detected\n"); + reset_irq(chan); + return -1; + } + reset_irq(chan); + return 0; +} + +/* Get the revision of the DMA module + * PARAMETER + * minor: Address of minor revision to write + * major: Address of major revision to write + * + * RETURN of non-zero means error + */ +int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) +{ + uint32_t val; + + /* debug information */ + val = readl(&dma4_cfg->revision); + *major = (val & 0x000000F0) >> 4; + *minor = (val & 0x0000000F); + debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor); + return 0; +} + +/* Initial config of omap dma + */ +void omap3_dma_init(void) +{ + dma_active = 0; + /* All interrupts on channel 0 */ + writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]); +} + +/* set channel config to config + * + * RETURN of non-zero means error */ +int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config) +{ + if (check_channel(chan)) + return -EINVAL; + + dma4_cfg->chan[chan] = *config; + return 0; +} + +/* get channel config to config + * + * RETURN of non-zero means error */ +int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config) +{ + if (check_channel(chan)) + return -EINVAL; + *config = dma4_cfg->chan[chan]; + return 0; +} |