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authorYork Sun <yorksun@freescale.com>2014-02-10 13:59:44 -0800
committerTom Rini <trini@ti.com>2014-02-21 11:06:13 -0500
commit6b1e1254f326940e5b65c7029f71b964bdf28fd4 (patch)
treea8e596b2d01fe4a952e253b9b42972b040a4a165 /drivers/ddr/fsl/util.c
parent6b9e309a8a7f0f33252288f0ed8794a83a488301 (diff)
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driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/util.c')
-rw-r--r--drivers/ddr/fsl/util.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 450a488..ad53658 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -228,6 +228,9 @@ void board_add_ram_info(int use_default)
puts(" DDR Controller Interleaving Mode: ");
switch ((cs0_config >> 24) & 0xf) {
+ case FSL_DDR_256B_INTERLEAVING:
+ puts("256B");
+ break;
case FSL_DDR_CACHE_LINE_INTERLEAVING:
puts("cache line");
break;