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| author | York Sun <yorksun@freescale.com> | 2015-07-23 14:04:48 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-08-03 12:06:38 -0700 |
| commit | 56848428a88f89420ae7acc04bb5805e70c430a3 (patch) | |
| tree | dacf689050c9dacae1c7ad899704298f6a7626c3 /drivers/ddr/fsl/main.c | |
| parent | 14d5547cf158c18bc340f01424e011b0802a6bb0 (diff) | |
| download | u-boot-imx-56848428a88f89420ae7acc04bb5805e70c430a3.zip u-boot-imx-56848428a88f89420ae7acc04bb5805e70c430a3.tar.gz u-boot-imx-56848428a88f89420ae7acc04bb5805e70c430a3.tar.bz2 | |
drivers/ddr/fsl: Adjust bstopre value
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 14ecf12..72ec1be 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -535,7 +535,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * which is currently STEP_ASSIGN_ADDRESSES. */ populate_memctl_options( - timing_params[i].all_dimms_registered, + &timing_params[i], &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); /* |