From 56848428a88f89420ae7acc04bb5805e70c430a3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 23 Jul 2015 14:04:48 -0700 Subject: drivers/ddr/fsl: Adjust bstopre value By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: York Sun --- drivers/ddr/fsl/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/ddr/fsl/main.c') diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 14ecf12..72ec1be 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -535,7 +535,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * which is currently STEP_ASSIGN_ADDRESSES. */ populate_memctl_options( - timing_params[i].all_dimms_registered, + &timing_params[i], &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); /* -- cgit v1.1