diff options
| author | Simon Glass <sjg@chromium.org> | 2016-11-13 14:22:13 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-11-25 17:59:31 -0700 |
| commit | 3a8a42d9550cf6779495037ce19c5357eed5ff88 (patch) | |
| tree | 5b829473194cd6dc1d9f013b839903be892e4ec5 /drivers/clk | |
| parent | aede3acc9cd68fc288ded462568d00e8615550a2 (diff) | |
| download | u-boot-imx-3a8a42d9550cf6779495037ce19c5357eed5ff88.zip u-boot-imx-3a8a42d9550cf6779495037ce19c5357eed5ff88.tar.gz u-boot-imx-3a8a42d9550cf6779495037ce19c5357eed5ff88.tar.bz2 | |
rockchip: clk: Support setting ACLK
Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3288.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index ed97e87..d15504c 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); switch (clk->id) { + case PLL_APLL: + /* We only support a fixed rate here */ + if (rate != 1800000000) + return -EINVAL; + rk3288_clk_configure_cpu(priv->cru, priv->grf); + new_rate = rate; + break; case CLK_DDR: new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); break; |