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author | Wolfgang Denk <wd@denx.de> | 2011-12-01 23:58:11 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-12-01 23:58:11 +0100 |
commit | d51e6d6de2b7dcba43fadcae2c89f7346d8bc301 (patch) | |
tree | 49bedf2073e031a421c89644f62134bf9ee4f44b /drivers/block/fsl_sata.c | |
parent | 22e0f5a9ecab85f36a0fe69892d950c1ac212c91 (diff) | |
parent | 9839709ea3df89f6021034508f48b97cab33ebb8 (diff) | |
download | u-boot-imx-d51e6d6de2b7dcba43fadcae2c89f7346d8bc301.zip u-boot-imx-d51e6d6de2b7dcba43fadcae2c89f7346d8bc301.tar.gz u-boot-imx-d51e6d6de2b7dcba43fadcae2c89f7346d8bc301.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
mpc85xx: support for Freescale COM Express P2020
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
mpc85xx: support board-specific reset function
powerpc/85xx: verify the localbus device tree address before booting the OS
mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
powerpc/p3060qds: Add board related support for P3060QDS platform
powerpc/85xx: clean up and document the QE/FMAN microcode macros
powerpc/85xx: always implement the work-around for Erratum SATA_A001
powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
powerpc/85xx: Add workaround for erratum A-003474
powerpc/85xx: fixup flexcan device tree clock-frequency
powerpc/85xx: Add workaround for erratum CPU-A003999
Diffstat (limited to 'drivers/block/fsl_sata.c')
-rw-r--r-- | drivers/block/fsl_sata.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 6b35173..3026ade 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -197,27 +197,6 @@ int init_sata(int dev) /* Wait the controller offline */ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000); -#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) - /* - * For P1022/1013 Rev1.0 silicon, after power on SATA host - * controller is configured in legacy mode instead of the - * expected enterprise mode. software needs to clear bit[28] - * of HControl register to change to enterprise mode from - * legacy mode. - */ - { - u32 svr = get_svr(); - if (IS_SVR_REV(svr, 1, 0) && - ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { - out_le32(®->hstatus, 0x20000000); - out_le32(®->hcontrol, 0x00000100); - } - } -#endif - /* Set the command header base address to CHBA register to tell DMA */ out_le32(®->chba, (u32)cmd_hdr & ~0x3); |