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authorKumar Gala <galak@kernel.crashing.org>2010-07-14 10:04:21 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-26 13:16:08 -0500
commit79e4e6480b359cb28129cecfa2cae0ef9cccf803 (patch)
tree45345be233f602736fd7df42c579b1b3abab6768 /doc
parentfd3c9befa83eecf6e7c6ef03c501159fbf754143 (diff)
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powerpc/8xxx: Enabled hwconfig for memory interleaving
Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.fsl-ddr25
1 files changed, 14 insertions, 11 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 9c2224f..6e4f6e9 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -32,38 +32,41 @@ The ways to configure the ddr interleaving mode
1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
under "CONFIG_EXTRA_ENV_SETTINGS", like:
#define CONFIG_EXTRA_ENV_SETTINGS \
- "memctl_intlv_ctl=2\0" \
+ "hwconfig=fsl_ddr:ctlr_intlv=bank" \
......
2. Run u-boot "setenv" command to configure the memory interleaving mode.
Either numerical or string value is accepted.
# disable memory controller interleaving
- setenv memctl_intlv_ctl
+ setenv hwconfig "fsl_ddr:ctlr_intlv=null"
# cacheline interleaving
- setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
+ setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
# page interleaving
- setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
+ setenv hwconfig "fsl_ddr:ctlr_intlv=page"
# bank interleaving
- setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
+ setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
# superbank
- setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
+ setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
# disable bank (chip-select) interleaving
- setenv ba_intlv_ctl
+ setenv hwconfig "fsl_ddr:bank_intlv=null"
# bank(chip-select) interleaving cs0+cs1
- setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
+ setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
# bank(chip-select) interleaving cs2+cs3
- setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
+ setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
# bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
- setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
+ setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
- setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3
+ setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
+
+ The above memory controller interleaving and bank interleaving can be mixed. The syntax is
+ setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"