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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-07-07 11:38:44 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-07-07 11:38:44 +0200 |
commit | 6f43ba70d15e15a08c25b3d956c70addb6740737 (patch) | |
tree | e5ddc8498043c0c47559737ea60e4d7fc866e20a /doc/device-tree-bindings | |
parent | 003b09dad492ebc385b28067b8028a0c0ff9323f (diff) | |
parent | 9c6b05cb724e18d1db3f9e1a75b2272572f06fbd (diff) | |
download | u-boot-imx-6f43ba70d15e15a08c25b3d956c70addb6740737.zip u-boot-imx-6f43ba70d15e15a08c25b3d956c70addb6740737.tar.gz u-boot-imx-6f43ba70d15e15a08c25b3d956c70addb6740737.tar.bz2 |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r-- | doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 31 | ||||
-rw-r--r-- | doc/device-tree-bindings/misc/intel,irq-router.txt | 50 | ||||
-rw-r--r-- | doc/device-tree-bindings/root.txt | 4 |
3 files changed, 85 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt new file mode 100644 index 0000000..45ab1af --- /dev/null +++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt @@ -0,0 +1,31 @@ +Intel x86 PINCTRL/GPIO controller + +Pin-muxing on x86 can be described with a node for the PINCTRL master +node and a set of child nodes for each pin on the SoC. + +The PINCTRL master node requires the following properties: +- compatible : "intel,x86-pinctrl" + +Pin nodes must be children of the pinctrl master node and can +contain the following properties: +- pad-offset - (required) offset in the IOBASE for the pin to configured. +- gpio-offset - (required) offset in the GPIOBASE for the pin to configured and + also the bit shift in this register. +- mode-gpio - (optional) standalone property to force the pin into GPIO mode. +- mode-func - (optional) function number to assign to the pin. if 'mode-gpio' + is set, this property will be ignored. +in case of 'mode-gpio' property set: +- output-value - (optional) this set the default output value of the GPIO. +- direction - (optional) this set the direction of the gpio. +- pull-str - (optional) this set the pull strength of the pin. +- pull-assign - (optional) this set the pull assignement (up/down) of the pin. + +Example: + +pin_usb_host_en0@0 { + gpio-offset = <0x80 8>; + pad-offset = <0x260>; + mode-gpio; + output-value = <1>; + direction = <PIN_OUTPUT>; +}; diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt new file mode 100644 index 0000000..598b4b1 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -0,0 +1,50 @@ +Intel Interrupt Router Device Binding +===================================== + +The device tree node which describes the operation of the Intel Interrupt Router +device is as follows: + +Required properties : +- reg : Specifies the interrupt router's PCI configuration space address as + defined by the Open Firmware spec. +- compatible = "intel,irq-router" +- intel,pirq-config : Specifies the IRQ routing register programming mechanism. + Valid values are: + "pci": IRQ routing is controlled by PCI configuration registers + "ibase": IRQ routing is in the memory-mapped IBASE register block +- intel,ibase-offset : IBASE register offset in the interrupt router's PCI + configuration space, required only if intel,pirq-config = "ibase". +- intel,pirq-link : Specifies the PIRQ link information with two cells. The + first cell is the register offset that controls the first PIRQ link routing. + The second cell is the total number of PIRQ links the router supports. +- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC. + Bit N is 1 means IRQ N is available to be routed. +- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, + encoded as 3 cells a group for a device. The first cell is the device's PCI + bus number, device number and function number encoding with PCI_BDF() macro. + The second cell is the PCI interrupt pin used by this device. The last cell + is which PIRQ line the PCI interrupt pin is routed to. + + +Example +------- + +#include <dt-bindings/interrupt-router/intel-irq.h> + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQB + PCI_BDF(0, 8, 0) INTA PIRQC + PCI_BDF(0, 8, 1) INTB PIRQD + PCI_BDF(1, 6, 0) INTA PIRQE + PCI_BDF(1, 6, 1) INTB PIRQF + PCI_BDF(1, 6, 2) INTC PIRQG + PCI_BDF(1, 6, 3) INTD PIRQH + >; + }; diff --git a/doc/device-tree-bindings/root.txt b/doc/device-tree-bindings/root.txt new file mode 100644 index 0000000..001ccf3 --- /dev/null +++ b/doc/device-tree-bindings/root.txt @@ -0,0 +1,4 @@ +The root node + +Optional properties: + - serial-number : a string representing the device's serial number |