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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-05-20 10:28:48 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-05-26 14:14:49 +0200 |
| commit | ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3 (patch) | |
| tree | 0790b0a014580d7cdb7e7fc8ab713a199a7733d8 /doc/README.socfpga | |
| parent | 48dbc74ea53396e39b3f59ec1a0049444610f3dd (diff) | |
| download | u-boot-imx-ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3.zip u-boot-imx-ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3.tar.gz u-boot-imx-ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3.tar.bz2 | |
imx: dma: correct MXS_DMA_ALIGNMENT
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'doc/README.socfpga')
0 files changed, 0 insertions, 0 deletions