summaryrefslogtreecommitdiff
path: root/doc/README.mpc85xx-spin-table
diff options
context:
space:
mode:
authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:30 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:32 -0500
commitffd06e0231ac3fd0c5810f39f6e23527948df1c7 (patch)
tree7d648c2c312b9cc7a75c0350101aacc67afca399 /doc/README.mpc85xx-spin-table
parent3f0997b3255c1498ac92453aa3a7a1cc95914dfd (diff)
downloadu-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.zip
u-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.gz
u-boot-imx-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.bz2
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc/README.mpc85xx-spin-table')
-rw-r--r--doc/README.mpc85xx-spin-table26
1 files changed, 26 insertions, 0 deletions
diff --git a/doc/README.mpc85xx-spin-table b/doc/README.mpc85xx-spin-table
new file mode 100644
index 0000000..8da768a
--- /dev/null
+++ b/doc/README.mpc85xx-spin-table
@@ -0,0 +1,26 @@
+Spin table in cache
+=====================================
+As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
+DDR is initialized and U-boot relocates itself into DDR, the spin table is
+accessible for core 0. It is part of release.S, within 4KB range after
+__secondary_start_page. For other cores to use the spin table, the booting
+process is described below:
+
+Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
+is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
+the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
+page translation for secondary cores to use this page of memory. Then 4KB
+memory is copied from __secondary_start_page to the boot page, after flusing
+cache because this page is mapped as normal DDR. Before copying the reset page,
+core 0 puts the physical address of the spin table (which is in release.S and
+relocated to the top of mapped memory) into a variable __spin_table_addr so
+that secondary cores can see it.
+
+When secondary cores boot up from 0xffff_f000 page, they only have one default
+TLB. While booting, they set up another TLB in AS=1 space and jump into
+the new space. The new TLB covers the physical address of the spin table page,
+with WIMGE =0b00100. Now secondary cores can keep polling the spin table
+without stress DDR bus because both the code and the spin table is in cache.
+
+For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep
+cache coherence.