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| author | Aneesh Bansal <aneesh.bansal@nxp.com> | 2016-04-18 22:58:33 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-24 10:31:21 -0700 |
| commit | 82eda68444fa4d026bcf1f59c7c0d044ddbcb193 (patch) | |
| tree | df6f6a6af8f690c3acc04ce23ad868ca700c3535 /doc/README.marubun-pcmcia | |
| parent | 46caebc1dff8f456b4f076bbebbb2ba32236d06d (diff) | |
| download | u-boot-imx-82eda68444fa4d026bcf1f59c7c0d044ddbcb193.zip u-boot-imx-82eda68444fa4d026bcf1f59c7c0d044ddbcb193.tar.gz u-boot-imx-82eda68444fa4d026bcf1f59c7c0d044ddbcb193.tar.bz2 | |
powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'doc/README.marubun-pcmcia')
0 files changed, 0 insertions, 0 deletions