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| author | Thierry Reding <treding@nvidia.com> | 2013-07-18 12:13:40 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-08-19 15:31:37 -0700 |
| commit | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde (patch) | |
| tree | 22fa69c5699349157e4c5848e84b13a9b2d6736c /doc/README.imx5 | |
| parent | 9ed887caecb9ecb0c68773a1870d143b9f28d3da (diff) | |
| download | u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.zip u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.tar.gz u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.tar.bz2 | |
ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'doc/README.imx5')
0 files changed, 0 insertions, 0 deletions