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authorOtavio Salvador <otavio@ossystems.com.br>2015-02-17 10:42:44 -0200
committerStefano Babic <sbabic@denx.de>2015-02-23 09:11:42 +0100
commitee0c538951018759eff4038db75e61b1cd040307 (patch)
tree612e1d55c9acee5252d0166b79fc99c32234ccd5 /doc/README.fsl-esdhc
parentf022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 (diff)
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mmc: fsl_esdhc: Add support to force VSELECT set
Some boards cannot do voltage negotiation but need to set the VSELECT bit forcely to ensure it to work at 1.8V. This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'doc/README.fsl-esdhc')
-rw-r--r--doc/README.fsl-esdhc1
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index b70f271..619c6b2 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -1,5 +1,6 @@
CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
+CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
Accessing ESDHC registers can be determined by ESDHC IP's endian
mode or processor's endian mode.