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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:26 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:29 -0500 |
| commit | a1d558a20f1eaeae9927abc4e0978725d33bae53 (patch) | |
| tree | 3af577ebb7be24efd3c23d7a8559512d2f9bfa70 /doc/README.bus_vcxk | |
| parent | eb5394120643922626f18e5fe7b0b3dc0ed43b9a (diff) | |
| download | u-boot-imx-a1d558a20f1eaeae9927abc4e0978725d33bae53.zip u-boot-imx-a1d558a20f1eaeae9927abc4e0978725d33bae53.tar.gz u-boot-imx-a1d558a20f1eaeae9927abc4e0978725d33bae53.tar.bz2 | |
powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc/README.bus_vcxk')
0 files changed, 0 insertions, 0 deletions