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authorwdenk <wdenk>2005-04-01 09:14:58 +0000
committerwdenk <wdenk>2005-04-01 09:14:58 +0000
commitf50cc09b613c5fab3b47079198ec476b7c227859 (patch)
tree0a051109a2b0cfec2fb10c0d9ee80b25378bcb83 /cpu
parentea287debe1980182adbe8c63b71bb82193dad5b7 (diff)
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Patch by Steven Scholz, 13 March 2005:
fix cache enabling for AT91RM9200
Diffstat (limited to 'cpu')
-rw-r--r--cpu/at91rm9200/start.S29
1 files changed, 14 insertions, 15 deletions
diff --git a/cpu/at91rm9200/start.S b/cpu/at91rm9200/start.S
index 43ab93d..0dbc009 100644
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -127,21 +127,20 @@ reset:
* is why it's called lowlevelinit
*/
bl lowlevelinit /* in lowlevel.S */
- bl icache_enable;
- /*------------------------------------
- Read/modify/write CP15 control register
- -------------------------------------
- read cp15 control register (cp15 r1) in r0
- ------------------------------------*/
- mrc p15, 0, r0, c1, c0, 0
- /* Reset bit :Little Endian end fast bus mode */
- ldr r3, =0xC0000080
- /* Set bit :Asynchronous clock mode, Not Fast Bus */
- ldr r4, =0xC0000000
- bic r0, r0, r3
- orr r0, r0, r4
- /* write r0 in cp15 control register (cp15 r1) */
- mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * Read/modify/write CP15 control register
+ * disable MMU, enable I-Cache, select Asychronous Clocking Mode
+ */
+
+ mrc p15, 0, r0, c1, c0, 0 @ read cp15 control register (cp15 r1) in r0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00000004 @ set bit 3 (C) D-Cache
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ orr r0, r0, #0xC0000000 @ set bits 31:30 (iA, nF)
+ mcr p15, 0, r0, c1, c0, 0 @ write r0 in cp15 control register (cp15 r1)
#endif /* CONFIG_BOOTBINFUNC */
/*
* relocate exeception table