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authorStefan Roese <sr@denx.de>2008-04-30 10:49:43 +0200
committerStefan Roese <sr@denx.de>2008-04-30 14:50:04 +0200
commitea9202a659dc75996facf1475f1866a19a9d3129 (patch)
tree648c80c047ae271af72089936135015c21ec2f1f /cpu
parent76617299358ebba260ecc02d33e8e75d8d13dd3b (diff)
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ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c
This patch fixes a problem with DIMMs that have 8 banks. Now the MCIF0_MBxCF register will be setup correctly for this setup too. This was noticed with the 512MB DIMM on Canyonlands/Glacier. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 5b5de48..ec76b71 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1,7 +1,10 @@
/*
* cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405: 405EX
+ * 440/460: 440SP/440SPe/460EX/460GT
*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
if (num_banks == 4)
ind = 0;
else
- ind = 5;
+ ind = 5 << 8;
switch (num_col_addr) {
case 0x08:
mode |= (SDRAM_BXCF_M_AM_0 + ind);