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authorTerry Lv <r65388@freescale.com>2010-03-18 18:43:28 +0800
committerTerry Lv <r65388@freescale.com>2010-03-19 11:16:53 +0800
commit8df54067b614e6debb4a4c4a89dd108c70b42e71 (patch)
treea7c5823b8b80081c2a8bb28192e3a765c6db8b32 /cpu
parent762d994929deb79569986bda8e4d7b56e06d14f0 (diff)
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ENGR00121731: Add mmu, l1cache, l2cache support for mx53
Add mmu, l1cache, l2cache support for mx53. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm_cortexa8/mx51/generic.c2
-rw-r--r--cpu/arm_cortexa8/mx53/generic.c19
2 files changed, 21 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
index 0762c03..eb1a023 100644
--- a/cpu/arm_cortexa8/mx51/generic.c
+++ b/cpu/arm_cortexa8/mx51/generic.c
@@ -26,7 +26,9 @@
#include <common.h>
#include <asm/arch/mx51.h>
#include <asm/errno.h>
+#ifdef CONFIG_ARCH_CPU_INIT
#include <asm/cache-cp15.h>
+#endif
#include "crm_regs.h"
enum pll_clocks {
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
index 01220c3..f75d15a 100644
--- a/cpu/arm_cortexa8/mx53/generic.c
+++ b/cpu/arm_cortexa8/mx53/generic.c
@@ -24,6 +24,9 @@
#include <asm/arch/mx53.h>
#include <asm/errno.h>
#include "crm_regs.h"
+#ifdef CONFIG_ARCH_CPU_INIT
+#include <asm/cache-cp15.h>
+#endif
enum pll_clocks {
PLL1_CLK = MXC_DPLL1_BASE,
@@ -336,6 +339,7 @@ int cpu_eth_init(bd_t *bis)
int rc = -ENODEV;
#if defined(CONFIG_MXC_FEC)
char *env = NULL;
+
rc = mxc_fec_initialize(bis);
env = getenv("fec_addr");
@@ -345,3 +349,18 @@ int cpu_eth_init(bd_t *bis)
return rc;
}
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+ icache_enable();
+ dcache_enable();
+
+#ifdef CONFIG_L2_OFF
+ l2_cache_disable();
+#else
+ l2_cache_enable();
+#endif
+ return 0;
+}
+#endif
+