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authorStefan Roese <sr@denx.de>2005-11-22 13:20:42 +0100
committerStefan Roese <sr@denx.de>2005-11-22 13:20:42 +0100
commit5568e613ee38d4bb5dd601cdb2f74ed0d7de9902 (patch)
treec89680cfc4931d8e0e3173c27959d678c3cbb44e /cpu
parentfe126d8b34d2e7c3c2dc1d4e61086018e016768c (diff)
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Add support for Prodrive P3P440 board:
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c - CFG_FLASH_QUIET_TEST added to use the common CFI driver for bank autodetection Patch by Stefan Roese, 22 Nov 2005
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/405gp_pci.c12
-rw-r--r--cpu/ppc4xx/sdram.c70
-rw-r--r--cpu/ppc4xx/start.S2
3 files changed, 81 insertions, 3 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 89be137..6a4128c 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -431,20 +431,24 @@ static struct pci_controller ppc440_hose = {0};
void pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
- unsigned long strap;
+#ifndef CONFIG_DISABLE_PISE_TEST
/*--------------------------------------------------------------------------+
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX)
+ unsigned long strap;
+
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
-#else
+#elif defined(CONFIG_440GP)
+ unsigned long strap;
+
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00040000) == 0 ){
printf("PCI: CPC0_STRP1[PISE] not set.\n");
@@ -452,6 +456,8 @@ void pci_440_init (struct pci_controller *hose)
return;
}
#endif
+#endif /* CONFIG_DISABLE_PISE_TEST */
+
/*--------------------------------------------------------------------------+
* PCI controller init
*--------------------------------------------------------------------------*/
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index d1ad212..e9548cd 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* (C) Copyright 2002-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
@@ -39,6 +42,7 @@ struct sdram_conf_s {
typedef struct sdram_conf_s sdram_conf_t;
+#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
@@ -46,9 +50,18 @@ sdram_conf_t mb0cf[] = {
{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#ifndef CONFIG_440
+
+/*
+ * Autodetect onboard SDRAM on 405 platforms
+ */
void sdram_init(void)
{
ulong sdtr1;
@@ -105,4 +118,61 @@ void sdram_init(void)
}
}
+#else /* CONFIG_440 */
+
+/*
+ * Autodetect onboard DDR SDRAM on 440 platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+long int initdram(int board_type)
+{
+ int i;
+
+ for (i=0; i<N_MB0CF; i++) {
+ /*
+ * Disable memory controller.
+ */
+ mtsdram(mem_cfg0, 0x00000000);
+
+ /*
+ * Setup some default
+ */
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, mb0cf[i].reg);
+ mtsdram(mem_tr0, 0x41094012);
+ mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*
+ * Enable the controller, then wait for DCEN to complete
+ */
+ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ udelay(10000);
+
+ if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ /*
+ * OK, size detected -> all done
+ */
+ return mb0cf[i].size;
+ }
+ }
+
+ return 0; /* nothing found ! */
+}
+
+#endif /* CONFIG_440 */
+
#endif /* CONFIG_SDRAM_BANK0 */
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index f434e20..8f7e817 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -444,6 +444,8 @@ __440gx_msr_continue:
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
+
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
#endif /* CONFIG_440 */