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authorMike Nuss <mike@terascala.com>2009-10-05 12:33:28 -0400
committerStefan Roese <sr@denx.de>2009-10-07 09:10:11 +0200
commit54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84 (patch)
tree049354d5e1f2fac5642865ee2078e6b8d29b4449 /cpu
parent99dbd4efd6d5ecc37d7e8f28b20d9be8c83055c7 (diff)
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PPC4xx: Denali core: Fix incorrect DDR row bits
The SPD detection code for the Denali memory controller used on some ppc4xx processors incorrectly encodes DDR0_42. With certain memory configurations, this can cause the bootwrapper to incorrectly calculate the installed memory size, because the number of row bits is wrong. This patch fixes that encoding. Signed-off-by: Mike Nuss <mike@terascala.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/denali_spd_ddr2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 4705e21..5858cb3 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1159,7 +1159,7 @@ phys_size_t initdram(int board_type)
mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
- mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+ mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,