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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-03-25 21:30:07 +0900
committerShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-03-25 21:30:07 +0900
commit373b16fc0c5ae34d28b9027f809ae3cbf45cdd15 (patch)
tree5032a9d3b00165d0ea5e19ae1b9584cdef2a6c45 /cpu
parentd98e348e2ed5aab8f7a6471ff628ab0688b8a459 (diff)
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[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mips/cache.S14
1 files changed, 9 insertions, 5 deletions
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index e6f3175..89ada71 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -1,5 +1,5 @@
/*
- * Cache-handling routined for MIPS 4K CPUs
+ * Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
@@ -32,10 +32,14 @@
#define RA t8
- /* 16KB is the maximum size of instruction and data caches on
- * MIPS 4K.
- */
-#define MIPS_MAX_CACHE_SIZE 0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x10000
#define INDEX_BASE KSEG0