Merge branch 'next' of ../master

136 files changed, 2983 insertions, 2190 deletions

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 7381da0..ade7f46 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -35,24 +35,8 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile
index 0e06f0a..1e49e8d 100644
--- a/cpu/arm1136/mx31/Makefile
+++ b/cpu/arm1136/mx31/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o generic.o
+COBJS	+= generic.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/timer.c
index ab7202f..29b484e 100644
--- a/cpu/arm1136/mx31/interrupts.c
+++ b/cpu/arm1136/mx31/timer.c
@@ -89,9 +89,8 @@ static inline unsigned long long us_to_tick(unsigned long long us)
 }
 #endif
 
-/* nothing really to do with interrupts, just starts up a counter. */
 /* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int interrupt_init (void)
+int timer_init (void)
 {
 	int i;
 
diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile
index f9afed7..48dc7e3 100644
--- a/cpu/arm1136/omap24xx/Makefile
+++ b/cpu/arm1136/omap24xx/Makefile
@@ -25,8 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o
-SOBJS	= start.o
+SOBJS	= reset.o
+
+COBJS	= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/reset.S
index 5f8343f..5f8343f 100644
--- a/cpu/arm1136/omap24xx/start.S
+++ b/cpu/arm1136/omap24xx/reset.S
diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/timer.c
index a0c535d..8dd8d7b 100644
--- a/cpu/arm1136/omap24xx/interrupts.c
+++ b/cpu/arm1136/omap24xx/timer.c
@@ -42,8 +42,7 @@
 static ulong timestamp;
 static ulong lastinc;
 
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
+int timer_init (void)
 {
 	int32_t val;
 
diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm1136/u-boot.lds
index ce979f3..7181a56 100644
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm1136/u-boot.lds
@@ -1,21 +1,15 @@
 /*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
  *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungin Park <kyugnmin.park@samsung.com>
  *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
+ * Copyright (c) 2004 Texas Instruments
  *
- * (C) Copyright 2002-2004
+ * (C) Copyright 2002
  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -35,23 +29,36 @@
  * MA 02111-1307 USA
  */
 
-#include <common.h>
-#include <arm926ejs.h>
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
 
-#ifdef CONFIG_INTEGRATOR
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm1136/start.o	(.text)
+		*(.text)
+	}
 
-	/* Timer functionality supplied by Integrator board (AP or CP) */
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-#else
+	. = ALIGN(4);
+	.data : { *(.data) }
 
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
-	extern void timer_init(void);
+	. = ALIGN(4);
+	.got : { *(.got) }
 
-	timer_init();
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
-	return 0;
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
 }
-
-#endif /* CONFIG_INTEGRATOR */
diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index fbc8ea8..c59a77b 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -38,11 +38,6 @@
 
 static void cache_flush (void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile
index fa4ee3f..4656d9a 100644
--- a/cpu/arm1176/s3c64xx/Makefile
+++ b/cpu/arm1176/s3c64xx/Makefile
@@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS-y	= interrupts.o
 COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
+COBJS-y	+= timer.o
 
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/timer.c
index 7bb9848..22a5b77 100644
--- a/cpu/arm1176/s3c64xx/interrupts.c
+++ b/cpu/arm1176/s3c64xx/timer.c
@@ -66,7 +66,7 @@ static unsigned long lastdec;
 /* Monotonic incrementing timer */
 static unsigned long long timestamp;
 
-int interrupt_init(void)
+int timer_init(void)
 {
 	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
 
diff --git a/cpu/arm1176/u-boot.lds b/cpu/arm1176/u-boot.lds
new file mode 100644
index 0000000..cc682f5
--- /dev/null
+++ b/cpu/arm1176/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm1176/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 6c40903..88c71bf 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -40,18 +40,6 @@
 static void cache_flush(void);
 #endif
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 39ed345..91d552c 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -110,9 +110,34 @@ static void timer_isr( void *data) {
 static ulong timestamp;
 static ulong lastdec;
 
-int interrupt_init (void)
+#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
+int arch_interrupt_init (void)
 {
+	int i;
+
+	/* install default interrupt handlers */
+	for ( i = 0; i < N_IRQS; i++) {
+		IRQ_HANDLER[i].m_data = (void *)i;
+		IRQ_HANDLER[i].m_func = default_isr;
+	}
+
+	/* configure interrupts for IRQ mode */
+	PUT_REG( REG_INTMODE, 0x0);
+	/* clear any pending interrupts */
+	PUT_REG( REG_INTPEND, 0x1FFFFF);
+
+	lastdec = 0;
+
+	/* install interrupt handler for timer */
+	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
+	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
+
+	return 0;
+}
+#endif
 
+int timer_init (void)
+{
 #if defined(CONFIG_NETARM)
 	/* disable all interrupts */
 	IRQEN = 0;
@@ -137,25 +162,6 @@ int interrupt_init (void)
 	/* set timer 1 counter */
 	lastdec = IO_TC1D = TIMER_LOAD_VAL;
 #elif defined(CONFIG_S3C4510B)
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
 	/* configure free running timer 0 */
 	PUT_REG( REG_TMOD, 0x0);
 	/* Stop timer 0 */
@@ -187,7 +193,7 @@ int interrupt_init (void)
 	PUT32(T0TCR, 1);	/* enable timer0 */
 
 #else
-#error No interrupt_init() defined for this CPU type
+#error No timer_init() defined for this CPU type
 #endif
 	timestamp = 0;
 
diff --git a/cpu/arm720t/u-boot.lds b/cpu/arm720t/u-boot.lds
new file mode 100644
index 0000000..111c3f5
--- /dev/null
+++ b/cpu/arm720t/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm720t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile
index 67f17fa..73aeeac 100644
--- a/cpu/arm920t/at91rm9200/Makefile
+++ b/cpu/arm920t/at91rm9200/Makefile
@@ -25,9 +25,17 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
-	  lxt972.o usb.o spi.o
-SOBJS	= lowlevel_init.o
+SOBJS	+= lowlevel_init.o
+
+COBJS	+= bcm5221.o
+COBJS	+= dm9161.o
+COBJS	+= ether.o
+COBJS	+= i2c.o
+COBJS	+= lxt972.o
+COBJS	+= reset.o
+COBJS	+= spi.o
+COBJS	+= timer.o
+COBJS	+= usb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c
index 9fd72d3..1711088 100644
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -189,14 +189,4 @@ i2c_init(int speed, int slaveaddr)
 	return;
 }
 
-int i2c_set_bus_speed(unsigned int speed)
-{
-	return -1;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
-	return CONFIG_SYS_I2C_SPEED;
-}
-
 #endif /* CONFIG_HARD_I2C */
diff --git a/cpu/arm920t/at91rm9200/reset.c b/cpu/arm920t/at91rm9200/reset.c
new file mode 100644
index 0000000..945ea2c
--- /dev/null
+++ b/cpu/arm920t/at91rm9200/reset.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void board_reset(void) __attribute__((__weak__));
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#if defined(CONFIG_AT91RM9200_USART)
+	/*shutdown the console to avoid strange chars during reset */
+	serial_exit();
+#endif
+
+	if (board_reset)
+		board_reset();
+
+	/* this is the way Linux does it */
+
+	/* FIXME:
+	 * These defines should be moved into
+	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+	 * as soon as the whitespace fix gets applied.
+	 */
+	#define AT91C_ST_RSTEN (0x1 << 16)
+	#define AT91C_ST_EXTEN (0x1 << 17)
+	#define AT91C_ST_WDRST (0x1 <<  0)
+	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
+	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
+
+	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	ST_CR = AT91C_ST_WDRST;
+
+	while (1);
+	/* Never reached */
+}
diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/timer.c
index cff4916..235d107 100644
--- a/cpu/arm920t/at91rm9200/interrupts.c
+++ b/cpu/arm920t/at91rm9200/timer.c
@@ -45,9 +45,7 @@ AT91PS_TC tmr;
 static ulong timestamp;
 static ulong lastinc;
 
-void board_reset(void) __attribute__((__weak__));
-
-int interrupt_init (void)
+int timer_init (void)
 {
 	tmr = AT91C_BASE_TC0;
 
@@ -160,38 +158,3 @@ ulong get_tbclk (void)
 	tbclk = CONFIG_SYS_HZ;
 	return tbclk;
 }
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * or toggle a GPIO pin on the AT91RM9200DK board
- */
-void reset_cpu (ulong ignored)
-{
-
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
-
-	if (board_reset)
-		board_reset();
-
-	/* this is the way Linux does it */
-
-	/* FIXME:
-	 * These defines should be moved into
-	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
-	 * as soon as the whitespace fix gets applied.
-	 */
-	#define AT91C_ST_RSTEN (0x1 << 16)
-	#define AT91C_ST_EXTEN (0x1 << 17)
-	#define AT91C_ST_WDRST (0x1 <<  0)
-	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
-	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
-
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-
-	while (1);
-	/* Never reached */
-}
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 0c080fe..34adb11 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -31,27 +31,10 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm920t.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile
index d3352de..28945e2 100644
--- a/cpu/arm920t/imx/Makefile
+++ b/cpu/arm920t/imx/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= generic.o interrupts.o speed.o
+COBJS	+= generic.o
+COBJS	+= speed.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/timer.c
index 1beaf9d..31ec588 100644
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/timer.c
@@ -32,10 +32,9 @@
 #include <common.h>
 #if defined (CONFIG_IMX)
 
-#include <arm920t.h>
 #include <asm/arch/imx-regs.h>
 
-int interrupt_init (void)
+int timer_init (void)
 {
 	int i;
 	/* setup GP Timer 1 */
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index 1fbd1f0..ea24cdf 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -30,7 +30,6 @@
  */
 
 #include <common.h>
-#include <arm920t.h>
 
 #ifdef CONFIG_USE_IRQ
 #include <asm/proc-armv/ptrace.h>
diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile
index f6b0063..f53fdc2 100644
--- a/cpu/arm920t/ks8695/Makefile
+++ b/cpu/arm920t/ks8695/Makefile
@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o
 SOBJS	= lowlevel_init.o
 
+COBJS	= timer.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/timer.c
index 883d689..22987bc 100644
--- a/cpu/arm920t/ks8695/interrupts.c
+++ b/cpu/arm920t/ks8695/timer.c
@@ -29,13 +29,13 @@
 #define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
 #define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
 
-int timer_inited;
 ulong timer_ticks;
 
-int interrupt_init (void)
+int timer_init (void)
 {
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
+	reset_timer();
+
+	return 0;
 }
 
 /*
@@ -53,7 +53,6 @@ void reset_timer_masked(void)
 	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
 	ks8695_write(KS8695_TIMER_CTRL, 0x2);
 	timer_ticks = 0;
-	timer_inited++;
 }
 
 void reset_timer(void)
@@ -87,9 +86,6 @@ void udelay(ulong usec)
 	ulong start = get_timer_masked();
 	ulong end;
 
-	if (!timer_inited)
-		reset_timer();
-
 	/* Only 1ms resolution :-( */
 	end = usec / 1000;
 	while (get_timer(start) < end)
diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile
index 3afe19c..5d2be2c 100644
--- a/cpu/arm920t/s3c24x0/Makefile
+++ b/cpu/arm920t/s3c24x0/Makefile
@@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o speed.o usb.o usb_ohci.o
+COBJS	+= speed.o
+COBJS	+= timer.o
+COBJS	+= usb.o
+COBJS	+= usb_ohci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/timer.c
index b8ce6ae..f0a09cd 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -32,7 +32,6 @@
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
 
-#include <arm920t.h>
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
@@ -52,7 +51,7 @@ static inline ulong READ_TIMER(void)
 static ulong timestamp;
 static ulong lastdec;
 
-int interrupt_init (void)
+int timer_init (void)
 {
 	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
 
diff --git a/cpu/arm920t/u-boot.lds b/cpu/arm920t/u-boot.lds
new file mode 100644
index 0000000..d9bfbee
--- /dev/null
+++ b/cpu/arm920t/u-boot.lds
@@ -0,0 +1,64 @@
+/*
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile
index 0d4912c..8d0e88f 100644
--- a/cpu/arm925t/Makefile
+++ b/cpu/arm925t/Makefile
@@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o omap925.o
+
+COBJS	+= cpu.o
+COBJS	+= omap925.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index 62828b1..71700bb 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -34,24 +34,8 @@
 #include <arm925t.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/timer.c
index 179992d..c16ef25 100644
--- a/cpu/arm925t/interrupts.c
+++ b/cpu/arm925t/timer.c
@@ -47,7 +47,7 @@ static uint32_t timestamp;
 static uint32_t lastdec;
 
 /* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
+int timer_init (void)
 {
 	/* Start the decrementer ticking down from 0xffffffff */
 	__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM);
diff --git a/cpu/arm925t/u-boot.lds b/cpu/arm925t/u-boot.lds
new file mode 100644
index 0000000..694780e
--- /dev/null
+++ b/cpu/arm925t/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm925t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile
index d5ac7d3..7701b03 100644
--- a/cpu/arm926ejs/Makefile
+++ b/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o
+COBJS	= cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile
index e300d97..66eec76 100644
--- a/cpu/arm926ejs/at91/Makefile
+++ b/cpu/arm926ejs/at91/Makefile
@@ -25,38 +25,16 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-ifdef CONFIG_AT91CAP9
-COBJS-$(CONFIG_MACB)		+= at91cap9_macb.o
-COBJS-y				+= at91cap9_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91cap9_spi.o
-endif
-ifdef CONFIG_AT91SAM9260
-COBJS-$(CONFIG_MACB)		+= at91sam9260_macb.o
-COBJS-y				+= at91sam9260_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91sam9260_spi.o
-endif
-ifdef CONFIG_AT91SAM9G20
-COBJS-$(CONFIG_MACB)		+= at91sam9260_macb.o
-COBJS-y				+= at91sam9260_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91sam9260_spi.o
-endif
-ifdef CONFIG_AT91SAM9261
-COBJS-y				+= at91sam9261_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91sam9261_spi.o
-endif
-ifdef CONFIG_AT91SAM9263
-COBJS-$(CONFIG_MACB)		+= at91sam9263_macb.o
-COBJS-y				+= at91sam9263_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91sam9263_spi.o
-COBJS-$(CONFIG_USB_OHCI_NEW)	+= at91sam9263_usb.o
-endif
-ifdef CONFIG_AT91SAM9RL
-COBJS-y				+= at91sam9rl_serial.o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= at91sam9rl_spi.o
-endif
+COBJS-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
+COBJS-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
+COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
+COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
+COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
+COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91_LED)	+= led.o
 COBJS-y += clock.o
 COBJS-y += cpu.o
+COBJS-y	+= reset.o
 COBJS-y	+= timer.o
 
 SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/cpu/arm926ejs/at91/at91cap9_spi.c b/cpu/arm926ejs/at91/at91cap9_devices.c
index cd8143b..c0024ac 100644
--- a/cpu/arm926ejs/at91/at91cap9_spi.c
+++ b/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -28,6 +28,54 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 
+void at91_serial0_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA22, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA23, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_HAS_DATAFLASH
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
 	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
@@ -98,3 +146,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 	}
 
 }
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
+#endif
+}
+#endif
diff --git a/cpu/arm926ejs/at91/at91cap9_macb.c b/cpu/arm926ejs/at91/at91cap9_macb.c
deleted file mode 100644
index 5095d8d..0000000
--- a/cpu/arm926ejs/at91/at91cap9_macb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_macb_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
-	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
-	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
-	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
-	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
-	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
-	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
-	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
-	at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
-	at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
-	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
-	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
-	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
-	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
-	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
-	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
-	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91cap9_serial.c b/cpu/arm926ejs/at91/at91cap9_serial.c
deleted file mode 100644
index 5f41f7e..0000000
--- a/cpu/arm926ejs/at91/at91cap9_serial.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PA22, 1);		/* TXD0 */
-	at91_set_A_periph(AT91_PIN_PA23, 0);		/* RXD0 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
-	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
-	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
-	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9260_spi.c b/cpu/arm926ejs/at91/at91sam9260_devices.c
index d6fd80e..5309ba2 100644
--- a/cpu/arm926ejs/at91/at91sam9260_spi.c
+++ b/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -28,6 +28,54 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 
+void at91_serial0_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_HAS_DATAFLASH
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
 	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
@@ -97,3 +145,40 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 		at91_set_gpio_output(AT91_PIN_PC3, 1);
 	}
 }
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
+	/*
+	 * use PA10, PA11 for ETX2, ETX3.
+	 * PA23 and PA24 are for TWI EEPROM
+	 */
+	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
+#else
+	at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
+#endif
+	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
+#endif
+}
+#endif
diff --git a/cpu/arm926ejs/at91/at91sam9260_macb.c b/cpu/arm926ejs/at91/at91sam9260_macb.c
deleted file mode 100644
index ea5e767..0000000
--- a/cpu/arm926ejs/at91/at91sam9260_macb.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_macb_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
-	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
-	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
-	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
-	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
-	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
-	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
-	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
-	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
-	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
-	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
-	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
-	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
-	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
-	/*
-	 * use PA10, PA11 for ETX2, ETX3.
-	 * PA23 and PA24 are for TWI EEPROM
-	 */
-	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
-	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
-#else
-	at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
-	at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
-#endif
-	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9260_serial.c b/cpu/arm926ejs/at91/at91sam9260_serial.c
deleted file mode 100644
index 43f1971..0000000
--- a/cpu/arm926ejs/at91/at91sam9260_serial.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
-	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
-	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
-	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
-	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9261_spi.c b/cpu/arm926ejs/at91/at91sam9261_devices.c
index 9383dc6..16d411f 100644
--- a/cpu/arm926ejs/at91/at91sam9261_spi.c
+++ b/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -28,6 +28,54 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 
+void at91_serial0_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC8, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC12, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PC13, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC14, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_HAS_DATAFLASH
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
 	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
@@ -97,3 +145,4 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 		at91_set_gpio_output(AT91_PIN_PA26, 1);
 	}
 }
+#endif
diff --git a/cpu/arm926ejs/at91/at91sam9261_serial.c b/cpu/arm926ejs/at91/at91sam9261_serial.c
deleted file mode 100644
index c262a92..0000000
--- a/cpu/arm926ejs/at91/at91sam9261_serial.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PC8, 1);		/* TXD0 */
-	at91_set_A_periph(AT91_PIN_PC9, 0);		/* RXD0 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PC12, 1);		/* TXD1 */
-	at91_set_A_periph(AT91_PIN_PC13, 0);		/* RXD1 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PC14, 1);		/* TXD2 */
-	at91_set_A_periph(AT91_PIN_PC15, 0);		/* RXD2 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
-	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9263_spi.c b/cpu/arm926ejs/at91/at91sam9263_devices.c
index e52dd61..0f2613e 100644
--- a/cpu/arm926ejs/at91/at91sam9263_spi.c
+++ b/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -28,6 +28,54 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 
+void at91_serial0_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA26, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA27, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_HAS_DATAFLASH
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
 	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
@@ -97,3 +145,40 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 		at91_set_gpio_output(AT91_PIN_PB18, 1);
 	}
 }
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* ETXCK_EREFCK */
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PE28, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
+#endif
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+void at91_uhp_hw_init(void)
+{
+	/* Enable VBus on UHP ports */
+	at91_set_gpio_output(AT91_PIN_PA21, 0);
+	at91_set_gpio_output(AT91_PIN_PA24, 0);
+}
+#endif
diff --git a/cpu/arm926ejs/at91/at91sam9263_macb.c b/cpu/arm926ejs/at91/at91sam9263_macb.c
deleted file mode 100644
index 4223d37..0000000
--- a/cpu/arm926ejs/at91/at91sam9263_macb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_macb_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PE21, 0);	/* ETXCK_EREFCK */
-	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ERXDV */
-	at91_set_A_periph(AT91_PIN_PE25, 0);	/* ERX0 */
-	at91_set_A_periph(AT91_PIN_PE26, 0);	/* ERX1 */
-	at91_set_A_periph(AT91_PIN_PE27, 0);	/* ERXER */
-	at91_set_A_periph(AT91_PIN_PE28, 0);	/* ETXEN */
-	at91_set_A_periph(AT91_PIN_PE23, 0);	/* ETX0 */
-	at91_set_A_periph(AT91_PIN_PE24, 0);	/* ETX1 */
-	at91_set_A_periph(AT91_PIN_PE30, 0);	/* EMDIO */
-	at91_set_A_periph(AT91_PIN_PE29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_A_periph(AT91_PIN_PE22, 0);	/* ECRS */
-	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
-	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
-	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
-	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
-	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
-	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
-	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9263_serial.c b/cpu/arm926ejs/at91/at91sam9263_serial.c
deleted file mode 100644
index 1076195..0000000
--- a/cpu/arm926ejs/at91/at91sam9263_serial.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PA26, 1);		/* TXD0 */
-	at91_set_A_periph(AT91_PIN_PA27, 0);		/* RXD0 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
-	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
-	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
-	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
diff --git a/cpu/arm926ejs/at91/at91sam9rl_serial.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 99ce418..ebed193 100644
--- a/cpu/arm926ejs/at91/at91sam9rl_serial.c
+++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -74,3 +74,40 @@ void at91_serial_hw_init(void)
 	at91_serial3_hw_init();
 #endif
 }
+
+#ifdef CONFIG_HAS_DATAFLASH
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_set_A_periph(AT91_PIN_PA25, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA26, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA27, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_A_periph(AT91_PIN_PA28, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_B_periph(AT91_PIN_PB7, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_A_periph(AT91_PIN_PD8, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_B_periph(AT91_PIN_PD9, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_gpio_output(AT91_PIN_PA28, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_gpio_output(AT91_PIN_PB7, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_gpio_output(AT91_PIN_PD8, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_gpio_output(AT91_PIN_PD9, 1);
+	}
+}
+#endif
diff --git a/cpu/arm926ejs/at91/at91sam9rl_spi.c b/cpu/arm926ejs/at91/at91sam9rl_spi.c
deleted file mode 100644
index 389d6d8..0000000
--- a/cpu/arm926ejs/at91/at91sam9rl_spi.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_set_A_periph(AT91_PIN_PA25, 0);	/* SPI0_MISO */
-	at91_set_A_periph(AT91_PIN_PA26, 0);	/* SPI0_MOSI */
-	at91_set_A_periph(AT91_PIN_PA27, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_A_periph(AT91_PIN_PA28, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_B_periph(AT91_PIN_PB7, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_A_periph(AT91_PIN_PD8, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_B_periph(AT91_PIN_PD9, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_gpio_output(AT91_PIN_PA28, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_gpio_output(AT91_PIN_PB7, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_gpio_output(AT91_PIN_PD8, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_gpio_output(AT91_PIN_PD9, 1);
-	}
-}
diff --git a/cpu/arm926ejs/at91/config.mk b/cpu/arm926ejs/at91/config.mk
index 06177e6..19296fd 100644
--- a/cpu/arm926ejs/at91/config.mk
+++ b/cpu/arm926ejs/at91/config.mk
@@ -1,2 +1 @@
 PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
-LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91/u-boot.lds
diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
index 2ae97fe..f2f7b62 100644
--- a/cpu/arm926ejs/at91/cpu.c
+++ b/cpu/arm926ejs/at91/cpu.c
@@ -21,17 +21,34 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
+#include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/io.h>
 
+#ifndef AT91_MAIN_CLOCK
+#define AT91_MAIN_CLOCK 0
+#endif
+
 int arch_cpu_init(void)
 {
-#ifdef AT91_MAIN_CLOCK
 	return at91_clock_init(AT91_MAIN_CLOCK);
-#else
-	return at91_clock_init(0);
-#endif
 }
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU: %s\n", AT91_CPU_NAME);
+	printf("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/cpu/arm926ejs/at91/at91sam9263_usb.c b/cpu/arm926ejs/at91/reset.c
index ff5593b..f963e14 100644
--- a/cpu/arm926ejs/at91/at91sam9263_usb.c
+++ b/cpu/arm926ejs/at91/reset.c
@@ -23,13 +23,20 @@
  */
 
 #include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
 #include <asm/arch/io.h>
 
-void at91_uhp_hw_init(void)
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out.
+ */
+void reset_cpu(ulong ignored)
 {
-	/* Enable VBus on UHP ports */
-	at91_set_gpio_output(AT91_PIN_PA21, 0);
-	at91_set_gpio_output(AT91_PIN_PA24, 0);
+	/* this is the way Linux does it */
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
+				     AT91_RSTC_PROCRST |
+				     AT91_RSTC_PERRST);
+
+	while (1);
+	/* Never reached */
 }
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
index c84cb5e..811bb3c 100644
--- a/cpu/arm926ejs/at91/timer.c
+++ b/cpu/arm926ejs/at91/timer.c
@@ -26,7 +26,6 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pit.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/io.h>
 #include <div64.h>
@@ -139,17 +138,3 @@ ulong get_tbclk(void)
 	tbclk = CONFIG_SYS_HZ;
 	return tbclk;
 }
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out.
- */
-void reset_cpu(ulong ignored)
-{
-	/* this is the way Linux does it */
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
-				     AT91_RSTC_PROCRST |
-				     AT91_RSTC_PERRST);
-
-	while (1);
-	/* Never reached */
-}
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 518c5e0..5c902df 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -31,27 +31,10 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm926ejs.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index ed24e65..6eaa89c 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -27,11 +27,19 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= timer.o ether.o lxt972.o dp83848.o
-SOBJS	= lowlevel_init.o reset.o
+COBJS-y				+= cpu.o timer.o psc.o
+COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
+COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
+COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+SOBJS	= reset.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	+= lowlevel_init.o
+endif
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(LIB)
diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk
new file mode 100644
index 0000000..a57d03a
--- /dev/null
+++ b/cpu/arm926ejs/davinci/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-msoft-float
+
+PLATFORM_CPPFLAGS += -march=armv5te
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c
new file mode 100644
index 0000000..29aead6
--- /dev/null
+++ b/cpu/arm926ejs/davinci/cpu.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL	0x100
+#define PLLC_PLLM	0x110
+#define PLLC_PREDIV	0x114
+#define PLLC_PLLDIV1	0x118
+#define PLLC_PLLDIV2	0x11c
+#define PLLC_PLLDIV3	0x120
+#define PLLC_POSTDIV	0x128
+#define PLLC_BPDIV	0x12c
+#define PLLC_PLLDIV4	0x160
+#define PLLC_PLLDIV5	0x164
+#define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV8	0x170
+#define PLLC_PLLDIV9	0x174
+
+#define BIT(x)		(1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM6447
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+
+static unsigned pll_div(volatile void *pllbase, unsigned offset)
+{
+	u32	div;
+
+	div = REG(pllbase + offset);
+	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	/* this register read seems to fail on pll0 */
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return 8;
+	else
+		return pll_div(pllbase, PLLC_PREDIV);
+#endif
+	return 1;
+}
+
+static inline unsigned pll_postdiv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+	return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+	volatile void	*pllbase = (volatile void *) pll_addr;
+	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+
+	/* the PLL might be bypassed */
+	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+		base /= pll_prediv(pllbase);
+		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+		base /= pll_postdiv(pllbase);
+	}
+	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
+}
+
+int print_cpuinfo(void)
+{
+	/* REVISIT fetch and display CPU ID and revision information
+	 * too ... that will matter as more revisions appear.
+	 */
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+
+#ifdef DSP_PLLDIV
+	printf(", DSP %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
+#endif
+
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
+				/ 2);
+	return 0;
+}
+
+#endif
+
diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c
new file mode 100644
index 0000000..bc45b67
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm355.c
@@ -0,0 +1,45 @@
+/*
+ * SoC-specific code for tms320dm355 and similar chips
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX3) |= (1 << 20) | (1 << 19);
+}
+#endif
diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c
new file mode 100644
index 0000000..bb105b5
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm644x.c
@@ -0,0 +1,96 @@
+/*
+ * SoC-specific code for tms320dm644x chips
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable EMAC. */
+	REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= PINMUX1_I2C;
+}
+#endif
+
+void davinci_errata_workarounds(void)
+{
+	/*
+	 * Workaround for TMS320DM6446 errata 1.3.22:
+	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+	 *   Revision(s) Affected: 1.3 and earlier
+	 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/*
+	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+	 * as suggested in TMS320DM6446 errata 2.1.2:
+	 *
+	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+	 * low priority modules can occupy the bus and prevent high priority
+	 * modules like the VPSS from getting the required DDR2 throughput.
+	 * A hex value of 0x20 should provide a good ARM (cache enabled)
+	 * performance and still allow good utilization by the VPSS or other
+	 * modules.
+	 */
+	REG(VBPR) = 0x20;
+}
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c
new file mode 100644
index 0000000..5bb972f
--- /dev/null
+++ b/cpu/arm926ejs/davinci/psc.c
@@ -0,0 +1,135 @@
+/*
+ * Power and Sleep Controller (PSC) functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * The PSC manages three inputs to a "module" which may be a peripheral or
+ * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
+ * its power domain.  For our purposes, we only care whether clock and power
+ * are active, and the module is out of reset.
+ *
+ * DaVinci chips may include two separate power domains: "Always On" and "DSP".
+ * Chips without a DSP generally have only one domain.
+ *
+ * The "Always On" power domain is always on when the chip is on, and is
+ * powered by the VDD pins (on DM644X). The majority of DaVinci modules
+ * lie within the "Always On" power domain.
+ *
+ * A separate domain called the "DSP" domain houses the C64x+ and other video
+ * hardware such as VICP. In some chips, the "DSP" domain is not always on.
+ * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
+ */
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01)
+		continue;
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	switch (id) {
+#ifdef CONFIG_SOC_DM644X
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	case DAVINCI_LPSC_VPSSSLV:
+	case DAVINCI_LPSC_EMAC:
+	case DAVINCI_LPSC_EMAC_WRAPPER:
+	case DAVINCI_LPSC_MDIO:
+	case DAVINCI_LPSC_USB:
+	case DAVINCI_LPSC_ATA:
+	case DAVINCI_LPSC_VLYNQ:
+	case DAVINCI_LPSC_UHPI:
+	case DAVINCI_LPSC_DDR_EMIF:
+	case DAVINCI_LPSC_AEMIF:
+	case DAVINCI_LPSC_MMC_SD:
+	case DAVINCI_LPSC_MEMSTICK:
+	case DAVINCI_LPSC_McBSP:
+	case DAVINCI_LPSC_GPIO:
+		*mdctl |= 0x200;
+		break;
+#endif
+	}
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03)
+		continue;
+	while ((*mdstat & 0x1f) != 0x03)	/* Probably an overkill... */
+		continue;
+}
+
+/* Not all DaVinci chips have a DSP power domain. */
+#ifdef CONFIG_SOC_DM644X
+
+/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+void dsp_on(void)
+{
+	int i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+#endif /* have a DSP */
diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S
index a687d44..ba0a7c3 100644
--- a/cpu/arm926ejs/davinci/reset.S
+++ b/cpu/arm926ejs/davinci/reset.S
@@ -50,6 +50,10 @@ reset_cpu:
 	str	r1, [r0]
 	ldr	r1, WDTCR_VAL2
 	str	r1, [r0]
+	/* Write an invalid value to the WDKEY field to trigger
+	 * an immediate watchdog reset */
+	mov     r1, $0x4000
+	str     r1, [r0]
 	nop
 	nop
 	nop
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 2604d57..80751ad 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -38,7 +38,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 typedef volatile struct {
 	u_int32_t	pid12;
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
index 960cf52..2870d24 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/cpu/arm926ejs/nomadik/timer.c
@@ -37,7 +37,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c
index 35ba7db..0052dab 100644
--- a/cpu/arm926ejs/omap/cpuinfo.c
+++ b/cpu/arm926ejs/omap/cpuinfo.c
@@ -11,7 +11,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm926ejs.h>
 
 #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
 
diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
index 97f9771..392b158 100644
--- a/cpu/arm926ejs/omap/timer.c
+++ b/cpu/arm926ejs/omap/timer.c
@@ -36,7 +36,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm926ejs/u-boot.lds b/cpu/arm926ejs/u-boot.lds
new file mode 100644
index 0000000..ee5eeb5
--- /dev/null
+++ b/cpu/arm926ejs/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm926ejs/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index 6697672..50c1335 100755
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -36,7 +36,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm946es/Makefile b/cpu/arm946es/Makefile
index d5ac7d3..e81f2da 100644
--- a/cpu/arm946es/Makefile
+++ b/cpu/arm946es/Makefile
@@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o
+
+COBJS	= cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index 04f0515..c63c98b 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -31,27 +31,10 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm946es.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c
deleted file mode 100644
index 3a16abe..0000000
--- a/cpu/arm946es/interrupts.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm946es.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-extern void reset_cpu(ulong addr);
-
-#ifdef CONFIG_INTEGRATOR
-	/* Timer functionality supplied by Integrator board (AP or CP) */
-#else
-
-static ulong timestamp;
-static ulong lastdec;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay(unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;         /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_raw (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	return get_timer_raw() / TIMER_LOAD_VAL;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-
-	if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ_CLOCK;    /* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;            /* finish normalize. */
-	}else{                          /* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ_CLOCK;
-		tmo /= (1000*1000);
-	}
-
-	reset_timer_masked ();	/* set "advancing" timestamp to 0, set lastdec vaule */
-
-	while (get_timer_raw () < tmo) /* wait for time stamp to overtake tick number.*/
-		/*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
-
-#endif /* CONFIG_INTEGRATOR */
diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S
index 9375c76..627e3cb 100644
--- a/cpu/arm946es/start.S
+++ b/cpu/arm946es/start.S
@@ -133,7 +133,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -192,6 +192,7 @@ _start_armboot:
  */
 
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -217,6 +218,7 @@ cpu_init_crit:
 	bl	lowlevel_init	/* go setup memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
+#endif
 /*
  *************************************************************************
  *
diff --git a/cpu/arm946es/u-boot.lds b/cpu/arm946es/u-boot.lds
new file mode 100644
index 0000000..5bd4390
--- /dev/null
+++ b/cpu/arm946es/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm946es/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index ca6bf4f..6fd07d0 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -36,29 +36,12 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 #ifndef CONFIG_L2_OFF
 void l2cache_disable(void);
 #endif
 
 static void cache_flush(void);
 
-int cpu_init(void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START =
-	    _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux(void)
 {
 	unsigned int i;
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..50176ee 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,14 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).a
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+
+COBJS	+= board.o
+COBJS	+= clock.o
+COBJS	+= gpio.o
+COBJS	+= mem.o
+COBJS	+= syslib.o
+COBJS	+= sys_info.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..6e29599 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -335,8 +335,8 @@ usage:
 U_BOOT_CMD(
 	nandecc, 2, 1,	do_switch_ecc,
 	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
-	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
-	);
+	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+);
 
 #endif /* CONFIG_NAND_OMAP_GPMC */
 
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index d035677..0306b6c 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -357,6 +357,28 @@ void per_clocks_enable(void)
 	sr32(&prcm_base->fclken_per, 11, 1, 0x1);
 	sr32(&prcm_base->iclken_per, 11, 1, 0x1);
 #endif
+
+#ifdef CONFIG_OMAP3_GPIO_2
+	sr32(&prcm_base->fclken_per, 13, 1, 1);
+	sr32(&prcm_base->iclken_per, 13, 1, 1);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_3
+	sr32(&prcm_base->fclken_per, 14, 1, 1);
+	sr32(&prcm_base->iclken_per, 14, 1, 1);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_4
+	sr32(&prcm_base->fclken_per, 15, 1, 1);
+	sr32(&prcm_base->iclken_per, 15, 1, 1);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_5
+	sr32(&prcm_base->fclken_per, 16, 1, 1);
+	sr32(&prcm_base->iclken_per, 16, 1, 1);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_6
+	sr32(&prcm_base->fclken_per, 17, 1, 1);
+	sr32(&prcm_base->iclken_per, 17, 1, 1);
+#endif
+
 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 	/* Turn on all 3 I2C clocks */
 	sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
diff --git a/cpu/arm_cortexa8/omap3/gpio.c b/cpu/arm_cortexa8/omap3/gpio.c
new file mode 100644
index 0000000..aeb6066
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/gpio.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+static struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
+
+static inline struct gpio_bank *get_gpio_bank(int gpio)
+{
+	return &gpio_bank[gpio >> 5];
+}
+
+static inline int get_gpio_index(int gpio)
+{
+	return gpio & 0x1f;
+}
+
+static inline int gpio_valid(int gpio)
+{
+	if (gpio < 0)
+		return -1;
+	if (gpio < 192)
+		return 0;
+	return -1;
+}
+
+static int check_gpio(int gpio)
+{
+	if (gpio_valid(gpio) < 0) {
+		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+		return -1;
+	}
+	return 0;
+}
+
+static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+{
+	void *reg = bank->base;
+	u32 l;
+
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		reg += OMAP24XX_GPIO_OE;
+		break;
+	default:
+		return;
+	}
+	l = __raw_readl(reg);
+	if (is_input)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_direction(int gpio, int is_input)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
+}
+
+static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+{
+	void *reg = bank->base;
+	u32 l = 0;
+
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		if (enable)
+			reg += OMAP24XX_GPIO_SETDATAOUT;
+		else
+			reg += OMAP24XX_GPIO_CLEARDATAOUT;
+		l = 1 << gpio;
+		break;
+	default:
+		printf("omap3-gpio unknown bank method %s %d\n",
+		       __FILE__, __LINE__);
+		return;
+	}
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_dataout(int gpio, int enable)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
+}
+
+int omap_get_gpio_datain(int gpio)
+{
+	struct gpio_bank *bank;
+	void *reg;
+
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+	bank = get_gpio_bank(gpio);
+	reg = bank->base;
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		reg += OMAP24XX_GPIO_DATAIN;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return (__raw_readl(reg)
+			& (1 << get_gpio_index(gpio))) != 0;
+}
+
+static void _reset_gpio(struct gpio_bank *bank, int gpio)
+{
+	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
+}
+
+int omap_request_gpio(int gpio)
+{
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void omap_free_gpio(int gpio)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+
+	_reset_gpio(bank, gpio);
+}
diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/timer.c
index 742fe9c..05cfe76 100644
--- a/cpu/arm_cortexa8/omap3/interrupts.c
+++ b/cpu/arm_cortexa8/omap3/timer.c
@@ -34,134 +34,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/proc-armv/ptrace.h>
-
-#ifdef CONFIG_USE_IRQ
-/* enable IRQ interrupts */
-void enable_interrupts(void)
-{
-	unsigned long temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
-			     ::"memory");
-}
-
-/*
- * disable IRQ/FIQ interrupts
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts(void)
-{
-	unsigned long old, temp;
-	__asm__ __volatile__("mrs %0, cpsr\n"
-			     "orr %1, %0, #0xc0\n"
-			     "msr cpsr_c, %1":"=r"(old), "=r"(temp)
-			     ::"memory");
-	return (old & 0x80) == 0;
-}
-#else
-void enable_interrupts(void)
-{
-	return;
-}
-int disable_interrupts(void)
-{
-	return 0;
-}
-#endif
-
-void bad_mode(void)
-{
-	panic("Resetting CPU ...\n");
-	reset_cpu(0);
-}
-
-void show_regs(struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-		"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
-		"UK4_26", "UK5_26", "UK6_26", "UK7_26",
-		"UK8_26", "UK9_26", "UK10_26", "UK11_26",
-		"UK12_26", "UK13_26", "UK14_26", "UK15_26",
-		"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
-		"UK4_32", "UK5_32", "UK6_32", "ABT_32",
-		"UK8_32", "UK9_32", "UK10_32", "UND_32",
-		"UK12_32", "UK13_32", "UK14_32", "SYS_32",
-	};
-
-	flags = condition_codes(regs);
-
-	printf("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer(regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
-	printf("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled(regs) ? "on" : "off",
-		fast_interrupts_enabled(regs) ? "on" : "off",
-		processor_modes[processor_mode(regs)],
-		thumb_mode(regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction(struct pt_regs *pt_regs)
-{
-	printf("undefined instruction\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_software_interrupt(struct pt_regs *pt_regs)
-{
-	printf("software interrupt\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_prefetch_abort(struct pt_regs *pt_regs)
-{
-	printf("prefetch abort\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_data_abort(struct pt_regs *pt_regs)
-{
-	printf("data abort\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_not_used(struct pt_regs *pt_regs)
-{
-	printf("not used\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_fiq(struct pt_regs *pt_regs)
-{
-	printf("fast interrupt request\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
-void do_irq(struct pt_regs *pt_regs)
-{
-	printf("interrupt request\n");
-	show_regs(pt_regs);
-	bad_mode();
-}
-
 
 static ulong timestamp;
 static ulong lastinc;
@@ -178,7 +50,7 @@ static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
 #define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
 #define TIMER_LOAD_VAL	0xffffffff
 
-int interrupt_init(void)
+int timer_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
 	writel(TIMER_LOAD_VAL, &timer_base->tldr);
diff --git a/cpu/arm926ejs/at91/u-boot.lds b/cpu/arm_cortexa8/u-boot.lds
index 8518a1d..4f1711c 100644
--- a/cpu/arm926ejs/at91/u-boot.lds
+++ b/cpu/arm_cortexa8/u-boot.lds
@@ -1,4 +1,7 @@
 /*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
  * (C) Copyright 2002
  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
@@ -22,7 +25,6 @@
  */
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
 OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
@@ -30,9 +32,9 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text :
+	.text	:
 	{
-		cpu/arm926ejs/start.o	(.text)
+		cpu/arm_cortexa8/start.o	(.text)
 		*(.text)
 	}
 
@@ -45,13 +47,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
 	__bss_start = .;
-	.bss : { *(.bss) . = ALIGN(4); }
+	.bss : { *(.bss) }
 	_end = .;
 }
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index b137f76..c0748e8 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -33,22 +33,6 @@
 #include <common.h>
 #include <command.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S
index 0031461..bb1f003 100644
--- a/cpu/arm_intcm/start.S
+++ b/cpu/arm_intcm/start.S
@@ -131,7 +131,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -188,11 +188,13 @@ _start_armboot:
  *************************************************************************
  */
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*  arm_int_generic assumes the ARM boot monitor, or user software,
 	 * has initialized the platform
 	 */
 	mov	pc, lr		/* back to my caller */
+#endif
 /*
  *************************************************************************
  *
diff --git a/cpu/arm_intcm/u-boot.lds b/cpu/arm_intcm/u-boot.lds
new file mode 100644
index 0000000..5eb87fb
--- /dev/null
+++ b/cpu/arm_intcm/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm_intcm/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/blackfin/system_map.S b/cpu/blackfin/system_map.S
deleted file mode 100644
index 286d7f3..0000000
--- a/cpu/blackfin/system_map.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * system_map.S - optional symbol lookup for debugging
- *
- * Copyright (c) 2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-
-#ifdef CONFIG_DEBUG_DUMP_SYMS
-.data
-.global _system_map
-.type _system_map,@object
-_system_map:
-#include SYM_FILE
-.asciz ""
-.size _system_map,.-_system_map
-#endif
diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
index 2121b0e..7e7c74c 100644
--- a/cpu/blackfin/traps.c
+++ b/cpu/blackfin/traps.c
@@ -171,38 +171,13 @@ void trap_c(struct pt_regs *regs)
 # define ENABLE_DUMP 0
 #endif
 
-#ifdef CONFIG_DEBUG_DUMP_SYMS
-# define ENABLE_DUMP_SYMS 1
-#else
-# define ENABLE_DUMP_SYMS 0
-#endif
-
-static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+#ifndef CONFIG_KALLSYMS
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
 {
-	if (!ENABLE_DUMP_SYMS)
-		return NULL;
-
-	extern const char system_map[] __attribute__((__weak__));
-	const char *sym, *csym;
-	char *esym;
-	unsigned long sym_addr;
-
-	sym = system_map;
-	csym = NULL;
-	*caddr = 0;
-
-	while (*sym) {
-		sym_addr = simple_strtoul(sym, &esym, 16);
-		sym = esym;
-		if (sym_addr > addr)
-			break;
-		*caddr = sym_addr;
-		csym = sym;
-		sym += strlen(sym) + 1;
-	}
-
-	return csym;
+	*caddr = addr;
+	return "N/A";
 }
+#endif
 
 static void decode_address(char *buf, unsigned long address)
 {
diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile
index 7e98d87..1403c4f 100644
--- a/cpu/ixp/Makefile
+++ b/cpu/ixp/Makefile
@@ -26,11 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
+
 COBJS-y	+= cpu.o
-COBJS-y	+= interrupts.o
-ifndef CONFIG_USE_IRQ
+COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
 COBJS-y	+= timer.o
-endif
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 42c62f6..ce275e5 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -38,10 +38,6 @@
 
 ulong loops_per_jiffy;
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -79,19 +75,6 @@ int print_cpuinfo (void)
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c
index 621f31b..06a826a 100644
--- a/cpu/ixp/interrupts.c
+++ b/cpu/ixp/interrupts.c
@@ -31,18 +31,8 @@
 
 #include <common.h>
 #include <asm/arch/ixp425.h>
-
-#ifdef CONFIG_USE_IRQ
 #include <asm/proc-armv/ptrace.h>
 
-/*
- * When interrupts are enabled, use timer 2 for time/delay generation...
- */
-
-#define FREQ		66666666
-#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
-
 struct _irq_handler {
 	void                *m_data;
 	void (*m_func)( void *data);
@@ -50,8 +40,6 @@ struct _irq_handler {
 
 static struct _irq_handler IRQ_HANDLER[N_IRQS];
 
-static volatile ulong timestamp;
-
 static void default_isr(void *data)
 {
 	printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
@@ -63,63 +51,32 @@ static int next_irq(void)
 	return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
 }
 
-static void timer_isr(void *data)
-{
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-
-	/*
-	 * Reset IRQ source
-	 */
-	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
-}
-
-ulong get_timer (ulong base)
+void do_irq (struct pt_regs *pt_regs)
 {
-	return timestamp - base;
-}
+	int irq = next_irq();
 
-void reset_timer (void)
-{
-	timestamp = 0;
+	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
 }
 
-#endif /* #ifdef CONFIG_USE_IRQ */
-
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
+void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
 {
-	int irq = next_irq();
+	if (irq >= N_IRQS || !handle_irq)
+		return;
 
-	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
+	IRQ_HANDLER[irq].m_data = data;
+	IRQ_HANDLER[irq].m_func = handle_irq;
 }
-#endif
 
-int interrupt_init (void)
+int arch_interrupt_init (void)
 {
-#ifdef CONFIG_USE_IRQ
 	int i;
 
 	/* install default interrupt handlers */
-	for (i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_data = (void *)&timestamp;
-	IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_func = timer_isr;
-
-	/* setup the Timer counter value */
-	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
+	for (i = 0; i < N_IRQS; i++)
+		irq_install_handler(i, default_isr, (void *)i);
 
 	/* configure interrupts for IRQ mode */
 	*IXP425_ICLR = 0x00000000;
 
-	/* enable timer irq */
-	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
-#endif
-
 	return (0);
 }
diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c
index deb227a..6856149 100644
--- a/cpu/ixp/timer.c
+++ b/cpu/ixp/timer.c
@@ -32,6 +32,54 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+#ifdef CONFIG_TIMER_IRQ
+
+#define FREQ		66666666
+#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
+#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
+
+/*
+ * When interrupts are enabled, use timer 2 for time/delay generation...
+ */
+
+static volatile ulong timestamp;
+
+static void timer_isr(void *data)
+{
+	unsigned int *pTime = (unsigned int *)data;
+
+	(*pTime)++;
+
+	/*
+	 * Reset IRQ source
+	 */
+	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
+}
+
+ulong get_timer (ulong base)
+{
+	return timestamp - base;
+}
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
+
+int timer_init (void)
+{
+	/* install interrupt handler for timer */
+	irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp);
+
+	/* setup the Timer counter value */
+	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
+
+	/* enable timer irq */
+	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
+
+	return 0;
+}
+#else
 ulong get_timer (ulong base)
 {
        return get_timer_masked () - base;
@@ -79,3 +127,9 @@ ulong get_timer_masked (void)
 	}
 	return (reload_constant - current);
 }
+
+int timer_init(void)
+{
+	return 0;
+}
+#endif
diff --git a/cpu/ixp/u-boot.lds b/cpu/ixp/u-boot.lds
new file mode 100644
index 0000000..85209ca
--- /dev/null
+++ b/cpu/ixp/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/ixp/start.o(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile
index bac2a64..1b3f58a 100644
--- a/cpu/lh7a40x/Makefile
+++ b/cpu/lh7a40x/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o interrupts.o serial.o
+COBJS	= cpu.o speed.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 338df87..b193189 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -31,27 +31,10 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm920t.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c
deleted file mode 100644
index 4767489..0000000
--- a/cpu/lh7a40x/serial.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONSOLE_UART1)
-# define UART_CONSOLE 1
-#elif defined(CONFIG_CONSOLE_UART2)
-# define UART_CONSOLE 2
-#elif defined(CONFIG_CONSOLE_UART3)
-# define UART_CONSOLE 3
-#else
-# error "No console configured ... "
-#endif
-
-void serial_setbrg (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-	int i;
-	unsigned int reg = 0;
-
-	/*
-	 * userguide 15.1.2.4
-	 *
-	 * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
-	 *
-	 *   UART_REF_FREQ = external system clock input / 2 (Hz)
-	 *   BAUD is desired baudrate (bits/s)
-	 *
-	 *   NOTE: we add (divisor/2) to numerator to round for
-	 *         more precision
-	 */
-	reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
-	uart->brcon = reg;
-
-	for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* UART must be enabled before writing to any config registers */
-	uart->con |= (UART_EN);
-
-#ifdef CONFIG_CONSOLE_UART1
-	/* infrared disabled */
-	uart->con |= UART_SIRD;
-#endif
-	/* loopback disabled */
-	uart->con &= ~(UART_LBE);
-
-	/* modem lines and tx/rx polarities */
-	uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
-
-	/* FIFO enable, N81 */
-	uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
-
-	/* set baudrate */
-	serial_setbrg ();
-
-	/* enable rx interrupt */
-	uart->inten |= UART_RI;
-
-	return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* wait for character to arrive */
-	while (uart->status & UART_RXFE);
-
-	return(uart->data & 0xff);
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
-	switch(on) {
-	case 0:
-	default:
-		break; /* return current */
-	case 1:
-		hwflow = 1; /* turn on */
-		break;
-	case -1:
-		hwflow = 0; /* turn off */
-		break;
-	}
-	return hwflow;
-}
-#endif
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet = 0;
-void disable_putc(void)
-{
-	be_quiet = 1;
-}
-
-void enable_putc(void)
-{
-	be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-#ifdef CONFIG_MODEM_SUPPORT
-	if (be_quiet)
-		return;
-#endif
-
-	/* wait for room in the tx FIFO */
-	while (!(uart->status & UART_TXFE));
-
-#ifdef CONFIG_HWFLOW
-	/* Wait for CTS up */
-	while(hwflow && !(uart->status & UART_CTS));
-#endif
-
-	uart->data = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	return(!(uart->status & UART_RXFE));
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/timer.c
index d39e707..f9b5be0 100644
--- a/cpu/lh7a40x/interrupts.c
+++ b/cpu/lh7a40x/timer.c
@@ -30,7 +30,6 @@
  */
 
 #include <common.h>
-#include <arm920t.h>
 #include <lh7a40x.h>
 
 static ulong timer_load_val = 0;
@@ -47,7 +46,7 @@ static inline ulong READ_TIMER(void)
 static ulong timestamp;
 static ulong lastdec;
 
-int interrupt_init (void)
+int timer_init (void)
 {
 	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
 	lh7a40x_timer_t* timer = &timers->timer1;
diff --git a/cpu/lh7a40x/u-boot.lds b/cpu/lh7a40x/u-boot.lds
new file mode 100644
index 0000000..e7543c9
--- /dev/null
+++ b/cpu/lh7a40x/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/lh7a40x/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile
index 297d135..022c676 100644
--- a/cpu/mpc512x/Makefile
+++ b/cpu/mpc512x/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2007 DENX Software Engineering
+# (C) Copyright 2007-2009 DENX Software Engineering
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -22,14 +22,20 @@
 
 include $(TOPDIR)/config.mk
 
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
-ifdef CONFIG_IIM
-COBJS	+= iim.o
-endif
-
+COBJS-y	:= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
+COBJS-${CONFIG_FSL_DIU_FB} += diu.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
+COBJS-${CONFIG_IIM} += iim.o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 START	:= $(addprefix $(obj),$(START))
diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h
new file mode 100644
index 0000000..4b14778
--- /dev/null
+++ b/cpu/mpc512x/asm-offsets.h
@@ -0,0 +1,15 @@
+/*
+ * needed for cpu/mpc512x/start.S
+ *
+ * These should be auto-generated
+ */
+#define LPCS0AW			0x0024
+#define SRAMBAR			0x00C4
+#define SWCRR			0x0904
+#define LPC_OFFSET		0x10000
+#define CS0_CONFIG		0x00000
+#define CS_CTRL			0x00020
+#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
+
+#define EXC_OFF_SYS_RESET	0x0100
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk
index 5b7e1f2..6ab34b1 100644
--- a/cpu/mpc512x/config.mk
+++ b/cpu/mpc512x/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2007 DENX Software Engineering
+# (C) Copyright 2007-2009 DENX Software Engineering
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -23,3 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
 			-ffixed-r2 -msoft-float -mcpu=603e
+
+# Use default linker script.
+# A board port can override this setting in board/*/config.mk
+LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index 8021bc1..42ccd81 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -29,7 +29,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <mpc512x.h>
 #include <net.h>
 #include <netdev.h>
 #include <asm/processor.h>
diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index fa753c8..fe6beaf 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * (C) Copyright 2007 DENX Software Engineering
+ * Copyright (C) 2007-2009 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,7 +25,8 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
+#include <asm/io.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,30 +47,34 @@ void cpu_init_f (volatile immap_t * im)
 
 #ifdef CONFIG_SYS_ACR_PIPE_DEP
 	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
-			  (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+	out_be32(&im->arbiter.acr,
+		(im->arbiter.acr & ~ACR_PIPE_DEP) |
+		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+	);
 #endif
 
 #ifdef CONFIG_SYS_ACR_RPTCNT
 	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
-			   (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+	out_be32(im->arbiter.acr,
+		(im->arbiter.acr & ~(ACR_RPTCNT)) |
+		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+	);
 #endif
 
 	/* RSR - Reset Status Register - clear all status */
 	gd->reset_status = im->reset.rsr;
-	im->reset.rsr = ~(RSR_RES);
+	out_be32(&im->reset.rsr, ~RSR_RES);
 
 	/*
 	 * RMR - Reset Mode Register - enable checkstop reset
 	 */
-	im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+	out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
 
 	/* Set IPS-CSB divider: IPS = 1/2 CSB */
-	ips_div = im->clk.scfr[0];
+	ips_div = in_be32(&im->clk.scfr[0]);
 	ips_div &= ~(SCFR1_IPS_DIV_MASK);
 	ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
-	im->clk.scfr[0] = ips_div;
+	out_be32(&im->clk.scfr[0], ips_div);
 
 	/*
 	 * Enable Time Base/Decrementer
@@ -78,7 +83,7 @@ void cpu_init_f (volatile immap_t * im)
 	 * have udelay() working; if not enabled, usually leads to a hang, like
 	 * during FLASH chip identification etc.
 	 */
-	im->sysconf.spcr |= SPCR_TBEN;
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 }
 
 int cpu_init_r (void)
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
new file mode 100644
index 0000000..70849ee
--- /dev/null
+++ b/cpu/mpc512x/diu.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "../../board/freescale/common/pixis.h"
+#include "../../board/freescale/common/fsl_diu_fb.h"
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
+
+#ifdef CONFIG_FSL_DIU_LOGO_BMP
+extern unsigned int FSL_Logo_BMP[];
+#else
+#define FSL_Logo_BMP NULL
+#endif
+
+static int xres, yres;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile clk512x_t *clk = &immap->clk;
+	volatile unsigned int *clkdvdr = &clk->scfr[0];
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0) * 4;
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
+	temp = *clkdvdr & 0xFFFFFF00;
+	*clkdvdr = temp | (pixval & 0xFF);
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
+}
+
+char *valid_bmp(char *addr)
+{
+	unsigned long h_addr;
+
+	h_addr = simple_strtoul(addr, NULL, 16);
+	if (h_addr < CONFIG_SYS_FLASH_BASE ||
+			h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+		printf("bmp addr %lx is not a valid flash address\n", h_addr);
+		return 0;
+	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
+		printf("bmp addr is not a bmp\n");
+		return 0;
+	} else
+		return (char *)h_addr;
+}
+
+int mpc5121_diu_init(void)
+{
+	unsigned int pixel_format;
+	char *bmp = NULL;
+	char *bmp_env;
+
+	xres = 1024;
+	yres = 768;
+	pixel_format = 0x88883316;
+
+	debug("mpc5121_diu_init\n");
+	bmp_env = getenv("diu_bmp_addr");
+	if (bmp_env) {
+		bmp = valid_bmp(bmp_env);
+	}
+	if (!bmp)
+		bmp = (char *)FSL_Logo_BMP;
+	return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
+}
+
+int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
+			     int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+
+	if (argc < 2) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if (!strncmp(argv[1], "init", 4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+		fsl_diu_clear_screen();
+		drv_video_init();
+#else
+		return mpc5121_diu_init();
+#endif
+	} else {
+		addr = simple_strtoul(argv[1], NULL, 16);
+		fsl_diu_clear_screen();
+		fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp,
+	"Init or Display BMP file",
+	"init\n    - initialize DIU\n"
+	"addr\n    - display bmp at address 'addr'"
+	);
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+	struct fb_info *info;
+
+	if (mpc5121_diu_init() < 0)
+		return;
+
+	/* fill in Graphic device struct */
+	sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
+		xres, yres, 32, 64, 60);
+
+	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+	pGD->winSizeX = xres;
+	pGD->winSizeY = yres - info->logo_height;
+	pGD->plnSizeX = pGD->winSizeX;
+	pGD->plnSizeY = pGD->winSizeY;
+
+	pGD->gdfBytesPP = 4;
+	pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+	pGD->isaBase = 0;
+	pGD->pciBase = 0;
+	pGD->memSize = info->screen_size - info->logo_size;
+
+	/* Cursor Start Address */
+	pGD->dprBase = 0;
+	pGD->vprBase = 0;
+	pGD->cprBase = 0;
+
+	return (void *)pGD;
+}
+
+/**
+  * Set the LUT
+  *
+  * @index: color number
+  * @r: red
+  * @b: blue
+  * @g: green
+  */
+void video_set_lut
+	(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+{
+	return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c
index 4f6bc86..e2d9097 100644
--- a/cpu/mpc512x/i2c.c
+++ b/cpu/mpc512x/i2c.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003 - 2007
+ * (C) Copyright 2003 - 2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -24,18 +24,16 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_HARD_I2C
 
-#include <mpc512x.h>
 #include <i2c.h>
 
-#define immr ((immap_t *)CONFIG_SYS_IMMR)
-
 /* by default set I2C bus 0 active */
-static unsigned int bus_num = 0;
+static unsigned int bus_num __attribute__ ((section (".data"))) = 0;
 
 #define I2C_TIMEOUT	100
 #define I2C_RETRIES	3
@@ -56,29 +54,24 @@ static int  mpc_get_fdr(int);
 
 static int mpc_reg_in (volatile u32 *reg)
 {
-	int ret = *reg >> 24;
-	__asm__ __volatile__ ("eieio");
+	int ret = in_be32(reg) >> 24;
+
 	return ret;
 }
 
 static void mpc_reg_out (volatile u32 *reg, int val, int mask)
 {
-	int tmp;
-
 	if (!mask) {
-		*reg = val << 24;
+		out_be32(reg, val << 24);
 	} else {
-		tmp = mpc_reg_in (reg);
-		*reg = ((tmp & ~mask) | (val & mask)) << 24;
+		clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
 	}
-	__asm__ __volatile__ ("eieio");
-
-	return;
 }
 
 static int wait_for_bb (void)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int timeout = I2C_TIMEOUT;
 	int status;
 
@@ -101,7 +94,8 @@ static int wait_for_bb (void)
 
 static int wait_for_pin (int *status)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int timeout = I2C_TIMEOUT;
 
 	*status = mpc_reg_in (&regs->msr);
@@ -122,7 +116,8 @@ static int wait_for_pin (int *status)
 
 static int do_address (uchar chip, char rdwr_flag)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int status;
 
 	chip <<= 1;
@@ -147,7 +142,8 @@ static int do_address (uchar chip, char rdwr_flag)
 
 static int send_bytes (uchar chip, char *buf, int len)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int wrcount;
 	int status;
 
@@ -170,7 +166,8 @@ static int send_bytes (uchar chip, char *buf, int len)
 
 static int receive_bytes (uchar chip, char *buf, int len)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int dummy   = 1;
 	int rdcount = 0;
 	int status;
@@ -208,9 +205,12 @@ static int receive_bytes (uchar chip, char *buf, int len)
 
 void i2c_init (int speed, int saddr)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	int i;
-	for(i = 0; i < I2C_BUS_CNT; i++){
-		i2c512x_dev_t *regs = &immr->i2c.dev[i];
+
+	for (i = 0; i < I2C_BUS_CNT; i++){
+		volatile i2c512x_dev_t *regs = &im->i2c.dev[i];
+
 		mpc_reg_out (&regs->mcr, 0, 0);
 
 		/* Set clock */
@@ -223,10 +223,10 @@ void i2c_init (int speed, int saddr)
 	}
 
 	/* Disable interrupts */
-	immr->i2c.icr = 0;
+	out_be32(&im->i2c.icr, 0);
+
 	/* Turn off filters */
-	immr->i2c.mifr = 0;
-	return;
+	out_be32(&im->i2c.mifr, 0);
 }
 
 static int mpc_get_fdr (int speed)
@@ -281,7 +281,8 @@ static int mpc_get_fdr (int speed)
 
 int i2c_probe (uchar chip)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int i;
 
 	for (i = 0; i < I2C_RETRIES; i++) {
@@ -302,8 +303,9 @@ int i2c_probe (uchar chip)
 
 int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	char xaddr[4];
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
 	int ret = -1;
 
 	xaddr[0] = (addr >> 24) & 0xFF;
@@ -346,8 +348,9 @@ Done:
 
 int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	char xaddr[4];
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
 	int ret = -1;
 
 	xaddr[0] = (addr >> 24) & 0xFF;
@@ -397,18 +400,4 @@ unsigned int i2c_get_bus_num (void)
 	return bus_num;
 }
 
-/* TODO */
-unsigned int i2c_get_bus_speed (void)
-{
-	return -1;
-}
-
-int i2c_set_bus_speed (unsigned int speed)
-{
-	if (speed != CONFIG_SYS_I2C_SPEED)
-		return -1;
-
-	return 0;
-}
-
 #endif	/* CONFIG_HARD_I2C */
diff --git a/cpu/mpc512x/ide.c b/cpu/mpc512x/ide.c
new file mode 100644
index 0000000..dd6b2f4
--- /dev/null
+++ b/cpu/mpc512x/ide.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_IDE_RESET)
+
+void ide_set_reset (int idereset)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	debug ("ide_set_reset(%d)\n", idereset);
+
+	if (idereset) {
+		out_be32(&im->pata.pata_ata_control, 0);
+	} else {
+		out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
+	}
+	udelay(100);
+}
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/*
+	 * Clear the reset bit to reset the interface
+	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+	 */
+	ide_set_reset(1);
+
+	/* Assert the reset bit to enable the interface */
+	ide_set_reset(0);
+
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	long t;
+	const struct {
+		short t0;
+		short t1;
+		short t2_8;
+		short t2_16;
+		short t2i;
+		short t4;
+		short t9;
+		short tA;
+	} pio_specs = {
+		.t0    = 600,
+		.t1    =  70,
+		.t2_8  = 290,
+		.t2_16 = 165,
+		.t2i   =   0,
+		.t4    =  30,
+		.t9    =  20,
+		.tA    =  50,
+	};
+	union {
+		u32 config;
+		struct {
+			u8 field1;
+			u8 field2;
+			u8 field3;
+			u8 field4;
+		}bytes;
+	} cfg;
+
+	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+		(u32)&im->pata);
+
+	/* Set the reset bit to 1 to enable the interface */
+	ide_set_reset(0);
+
+	/* Init timings : we use PIO mode 0 timings */
+	t = 1000000000 / gd->ips_clk;	/* period in ns */
+	cfg.bytes.field1 = 3;
+	cfg.bytes.field2 = 3;
+	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+	out_be32(&im->pata.pata_time1, cfg.config);
+
+	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+	cfg.bytes.field3 = 1;
+	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+	out_be32(&im->pata.pata_time2, cfg.config);
+
+	cfg.config = in_be32(&im->pata.pata_time3);
+	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+	out_be32(&im->pata.pata_time3, cfg.config);
+
+	debug ("PATA preinit complete.\n");
+
+	return 0;
+}
+
+#endif /* defined(CONFIG_IDE_RESET) */
diff --git a/cpu/mpc512x/iim.c b/cpu/mpc512x/iim.c
index 6cdc422..8f2eb37 100644
--- a/cpu/mpc512x/iim.c
+++ b/cpu/mpc512x/iim.c
@@ -389,6 +389,6 @@ U_BOOT_CMD(
 	"			    no args for entire bank\n"
 	"fuse prog <frow_bit> 	- program fuse at row <frow>, bit <_bit>\n"
 	"			    <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
-	"			  WARNING - this is permanent\n"
-	);
+	"			  WARNING - this is permanent"
+);
 #endif /* CONFIG_CMD_FUSE */
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
index 78f4fa1e..be20947 100644
--- a/cpu/mpc512x/iopin.c
+++ b/cpu/mpc512x/iopin.c
@@ -23,15 +23,15 @@
 
 #include <common.h>
 #include <linux/types.h>
-#include <mpc512x.h>
+#include <asm/io.h>
 
 void iopin_initialize(iopin_t *ioregs_init, int len)
 {
 	short i, j, p;
-	u_long *reg;
+	u32 *reg;
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-	reg = (u_long *)&(im->io_ctrl.regs[0]);
+	reg = (u32 *)&(im->io_ctrl);
 
 	if (sizeof(ioregs_init) == 0)
 		return;
@@ -40,9 +40,9 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
 		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
 			p < ioregs_init[i].nr_pins; p++, j++) {
 			if (ioregs_init[i].bit_or)
-				reg[j] |= ioregs_init[i].val;
+				setbits_be32(reg + j, ioregs_init[i].val);
 			else
-				reg[j] = ioregs_init[i].val;
+				out_be32 (reg + j, ioregs_init[i].val);
 		}
 	}
 	return;
diff --git a/cpu/mpc512x/pci.c b/cpu/mpc512x/pci.c
new file mode 100644
index 0000000..166a993
--- /dev/null
+++ b/cpu/mpc512x/pci.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ * Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile law512x_t *pci_law;
+	volatile pot512x_t *pci_pot;
+	volatile pcictrl512x_t *pci_ctrl;
+	volatile pciconf512x_t *pci_conf;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	int i;
+	struct pci_controller *hose;
+
+	/* Set PCI divider for 33MHz */
+	reg32 = im->clk.scfr[0];
+	reg32 &= ~(SCFR1_PCI_DIV_MASK);
+	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+	im->clk.scfr[0] = reg32;
+
+	clrsetbits_be32(&im->clk.scfr[0],
+			SCFR1_PCI_DIV_MASK,
+			SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
+	);
+
+	pci_law = im->sysconf.pcilaw;
+	pci_pot = im->ios.pot;
+	pci_ctrl = &im->pci_ctrl;
+	pci_conf = &im->pci_conf;
+
+	hose = &pci_hose;
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	out_be32(&pci_ctrl->gcr, 0);
+	udelay(2000);
+	out_be32(&pci_ctrl->gcr, 1);
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	for (i = 0; i < 1000; i++)
+		udelay(1000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
+
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	out_be32(&pci_pot[0].potar,
+		(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[0].pobar,
+		(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[0].pocmr,
+		POCMR_EN | POCMR_PRE | POCMR_CM_256M);
+
+	/* PCI IO space */
+	out_be32(&pci_pot[1].potar,
+		(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[1].pobar,
+		(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[1].pocmr,
+		POCMR_EN | POCMR_IO | POCMR_CM_16M);
+
+	/* PCI mmio - non-prefetch mem space */
+	out_be32(&pci_pot[2].potar,
+		(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[2].pobar,
+		(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[2].pocmr,
+		POCMR_EN | POCMR_CM_256M);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	out_be32(&pci_ctrl[0].pitar1, 0x0);
+	out_be32(&pci_ctrl[0].pibar1, 0x0);
+	out_be32(&pci_ctrl[0].piebar1, 0x0);
+	out_be32(&pci_ctrl[0].piwar1,
+		PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+		PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS,
+		       CONFIG_SYS_PCI_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CONFIG_SYS_IMMR + 0x8300),
+			   (CONFIG_SYS_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c
index 7db87a8..4fc4693 100644
--- a/cpu/mpc512x/serial.c
+++ b/cpu/mpc512x/serial.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000 - 2007
+ * (C) Copyright 2000 - 2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,6 +30,8 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,66 +42,73 @@ static void fifo_init (volatile psc512x_t *psc)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* reset Rx & Tx fifo slice */
-	psc->rfcmd = PSC_FIFO_RESET_SLICE;
-	psc->tfcmd = PSC_FIFO_RESET_SLICE;
+	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
 
 	/* disable Tx & Rx FIFO interrupts */
-	psc->rfintmask = 0;
-	psc->tfintmask = 0;
+	out_be32(&psc->rfintmask, 0);
+	out_be32(&psc->tfintmask, 0);
 
-	psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
-	psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+	out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
+	out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
 
 	/* enable Tx & Rx FIFO slice */
-	psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
-	psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
+	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
 
-	im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
+	out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
 	__asm__ volatile ("sync");
 }
 
+void serial_setbrg(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	unsigned long baseclk, div;
+
+	/* calculate dividor for setting PSC CTUR and CTLR registers */
+	baseclk = (gd->ips_clk + 8) / 16;
+	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+
+	out_8(&psc->ctur, (div >> 8) & 0xff);
+	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
+}
+
 int serial_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-	unsigned long baseclk;
-	int div;
 
 	fifo_init (psc);
 
 	/* set MR register to point to MR1 */
-	psc->command = PSC_SEL_MODE_REG_1;
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
 
 	/* disable Tx/Rx */
-	psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
+	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
 
 	/* choose the prescaler	by 16 for the Tx/Rx clock generation */
-	psc->psc_clock_select =  0xdd00;
+	out_be16(&psc->psc_clock_select, 0xdd00);
 
 	/* switch to UART mode */
-	psc->sicr = 0;
+	out_be32(&psc->sicr, 0);
 
 	/* mode register points to mr1 */
 	/* configure parity, bit length and so on in mode register 1*/
-	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
 	/* now, mode register points to mr2 */
-	psc->mode = PSC_MODE_1_STOPBIT;
-
-	/* calculate dividor for setting PSC CTUR and CTLR registers */
-	baseclk = (gd->ips_clk + 8) / 16;
-	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
 
-	psc->ctur = (div >> 8) & 0xff;
 	/* set baudrate */
-	psc->ctlr = div & 0xff;
+	serial_setbrg();
 
 	/* disable all interrupts */
-	psc->psc_imr = 0;
+	out_be16(&psc->psc_imr, 0);
 
 	/* reset and enable Rx/Tx */
-	psc->command = PSC_RST_RX;
-	psc->command = PSC_RST_TX;
-	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
 
 	return 0;
 }
@@ -113,7 +122,7 @@ void serial_putc (const char c)
 		serial_putc ('\r');
 
 	/* Wait for last character to go. */
-	while (!(psc->psc_status & PSC_SR_TXEMP))
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
 		;
 
 	psc->tfdata_8 = c;
@@ -125,7 +134,7 @@ void serial_putc_raw (const char c)
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
 	/* Wait for last character to go. */
-	while (!(psc->psc_status & PSC_SR_TXEMP))
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
 		;
 
 	psc->tfdata_8 = c;
@@ -145,7 +154,7 @@ int serial_getc (void)
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
 	/* Wait for a character to arrive. */
-	while (psc->rfstat & PSC_FIFO_EMPTY)
+	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
 		;
 
 	return psc->rfdata_8;
@@ -156,20 +165,7 @@ int serial_tstc (void)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
-	return !(psc->rfstat & PSC_FIFO_EMPTY);
-}
-
-void serial_setbrg (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-	unsigned long baseclk, div;
-
-	baseclk = (gd->csb_clk + 8) / 16;
-	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
-
-	psc->ctur = (div >> 8) & 0xFF;
-	psc->ctlr =  div & 0xff; /* set baudrate */
+	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
 }
 
 void serial_setrts(int s)
@@ -179,11 +175,11 @@ void serial_setrts(int s)
 
 	if (s) {
 		/* Assert RTS (become LOW) */
-		psc->op1 = 0x1;
+		out_8(&psc->op1, 0x1);
 	}
 	else {
 		/* Negate RTS (become HIGH) */
-		psc->op0 = 0x1;
+		out_8(&psc->op0, 0x1);
 	}
 }
 
@@ -192,6 +188,6 @@ int serial_getcts(void)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
-	return (psc->ip & 0x1) ? 0 : 1;
+	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
 }
 #endif /* CONFIG_PSC_CONSOLE */
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index 5992111..ce8d094 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2007
+ * (C) Copyright 2000-2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
@@ -26,8 +26,8 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <command.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -75,29 +75,37 @@ int get_clocks (void)
 	u32 csb_clk;
 	u32 ips_clk;
 	u32 pci_clk;
+	u32 reg;
 
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+	reg = in_be32(&im->sysconf.immrbar);
+	if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
-	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+	reg = in_be32(&im->clk.spmr);
+	spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 	spll = ref_clk * spmf_mult[spmf];
 
-	sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
+	reg = in_be32(&im->clk.scfr[1]);
+	sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
 	sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
 
 	csb_clk = sys_clk / 2;
 
-	cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+	reg = in_be32(&im->clk.spmr);
+	cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
 	core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
 
-	ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
+	reg = in_be32(&im->clk.scfr[0]);
+	ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
 	if (ips_div != 0) {
 		ips_clk = csb_clk / ips_div;
 	} else {
 		/* in case we cannot get a sane IPS divisor, fail gracefully */
 		ips_clk = 0;
 	}
-	pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+
+	reg = in_be32(&im->clk.scfr[0]);
+	pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
 	if (pci_div != 0) {
 		pci_clk = csb_clk / pci_div;
 	} else {
@@ -138,7 +146,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 	"print clock configuration",
-	"    clocks\n"
+	"    clocks"
 );
 
 int prt_mpc512x_clks (void)
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 360682d..178e5d1 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
  * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,12 +30,14 @@
  */
 
 #include <config.h>
-#include <mpc512x.h>
 #include <timestamp.h>
 #include <version.h>
 
 #define CONFIG_521X	1		/* needed for Linux kernel header files*/
 
+#include <asm/immap_512x.h>
+#include "asm-offsets.h"
+
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/cpu/mpc512x/u-boot.lds b/cpu/mpc512x/u-boot.lds
new file mode 100644
index 0000000..dae3269
--- /dev/null
+++ b/cpu/mpc512x/u-boot.lds
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc512x/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index 35cf8f1..d2bdcc2 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -58,9 +58,6 @@ static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
 #define	CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef	CONFIG_SYS_I2C_SLAVE
-#define	CONFIG_SYS_I2C_SLAVE	0xFE
-#endif
 /*-----------------------------------------------------------------------
  */
 
@@ -783,19 +780,6 @@ int i2c_set_bus_num(unsigned int bus)
 #endif
 	return 0;
 }
-/* TODO: add 100/400k switching */
-unsigned int i2c_get_bus_speed(void)
-{
-	return CONFIG_SYS_I2C_SPEED;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
-	if (speed != CONFIG_SYS_I2C_SPEED)
-		return -1;
-
-	return 0;
-}
 
 #endif	/* CONFIG_I2C_MULTI_BUS */
 #endif	/* CONFIG_HARD_I2C */
diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk
index 2f0f1ce..d619426 100644
--- a/cpu/mpc83xx/config.mk
+++ b/cpu/mpc83xx/config.mk
@@ -22,7 +22,7 @@
 
 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
-PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \
 			-ffixed-r2 -msoft-float
 
 # Use default linker script.  Board port can override in board/*/config.mk
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 876f5c7..c4331ae 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -367,24 +367,10 @@ int dma_xfer(void *dest, u32 count, void *src)
  */
 int cpu_eth_init(bd_t *bis)
 {
-#if defined(CONFIG_UEC_ETH1)
-	uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
-	uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
-	uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
-	uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
-	uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
-	uec_initialize(5);
+#if defined(CONFIG_UEC_ETH)
+	uec_standard_init(bis);
 #endif
+
 #if defined(CONFIG_TSEC_ENET)
 	tsec_standard_init(bis);
 #endif
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 8e9c875..414565c 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,6 +23,10 @@
 #include <common.h>
 #include <mpc83xx.h>
 #include <ioports.h>
+#ifdef CONFIG_USB_EHCI_FSL
+#include <asm/io.h>
+#include <usb/ehci-fsl.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -185,7 +189,7 @@ void cpu_init_f (volatile immap_t * im)
 
 	/* System General Purpose Register */
 #ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 	im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
 #else
@@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im)
 	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 #endif
+#ifdef CONFIG_USB_EHCI_FSL
+	uint32_t temp;
+	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+
+	/* Configure interface. */
+	setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+
+	/* Wait for clock to stabilize */
+	do {
+		temp = in_be32((void *)ehci->control);
+		udelay(1000);
+	} while (!(temp & PHY_CLK_VALID));
+#endif
 }
 
 int cpu_init_r (void)
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 9b7e7b5..bde7e92 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -100,23 +100,23 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
 #endif
-#ifdef CONFIG_MPC834X
+#ifdef CONFIG_MPC834x
 	u32 usbmph_clk;
 #endif
 	u32 core_clk;
 	u32 i2c1_clk;
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	u32 i2c2_clk;
 #endif
 #if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	u32 sdhc_clk;
 #endif
 	u32 enc_clk;
@@ -126,17 +126,17 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	u32 mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	u32 qepmf;
 	u32 qepdf;
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
 #endif
 
@@ -164,7 +164,7 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -202,7 +202,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -229,7 +229,7 @@ int get_clocks(void)
 		tsec2_clk = 0;
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 	case 0:
 		usbmph_clk = 0;
@@ -274,7 +274,7 @@ int get_clocks(void)
 		return -7;
 	}
 
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
 	case 0:
 		sdhc_clk = 0;
@@ -313,22 +313,22 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	i2c1_clk = tsec2_clk;
 #elif defined(CONFIG_MPC8360)
 	i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832X)
+#elif defined(CONFIG_MPC832x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC831x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 	i2c1_clk = sdhc_clk;
 #endif
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 	case 0:
 		pciexp1_clk = 0;
@@ -366,7 +366,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 	case 0:
 		sata_clk = 0;
@@ -436,7 +436,7 @@ int get_clocks(void)
 		return -13;
 	}
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
 	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -444,23 +444,23 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	gd->usbmph_clk = usbmph_clk;
 #endif
 #if defined(CONFIG_MPC8315)
 	gd->tdm_clk = tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	gd->sdhc_clk = sdhc_clk;
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
 	gd->enc_clk = enc_clk;
@@ -470,15 +470,15 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	gd->mem_sec_clk = mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	gd->pciexp1_clk = pciexp1_clk;
 	gd->pciexp2_clk = pciexp2_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	gd->sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
@@ -504,7 +504,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	printf("Clock configuration:\n");
 	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 #endif
@@ -516,28 +516,28 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #endif
 	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
 	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
 	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
 #endif
 	return 0;
@@ -545,5 +545,5 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 	"print clock configuration",
-	"    clocks\n"
+	"    clocks"
 );
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..d88c564 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
 struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(8533, 8533),
 	CPU_TYPE_ENTRY(8533, 8533_E),
+	CPU_TYPE_ENTRY(8535, 8535),
+	CPU_TYPE_ENTRY(8535, 8535_E),
 	CPU_TYPE_ENTRY(8536, 8536),
 	CPU_TYPE_ENTRY(8536, 8536_E),
 	CPU_TYPE_ENTRY(8540, 8540),
@@ -184,6 +186,10 @@ int checkcpu (void)
 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
 
+#ifdef CONFIG_QE
+	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+#endif
+
 	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 
 	return 0;
@@ -260,26 +266,28 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr0 = 0x02c40000;
-	dma->datr0 = 0x02c40000;
-	dma->sr0 = 0xfffffff; /* clear any errors */
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
 
 uint dma_check(void) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-	volatile uint status = dma->sr0;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
+	volatile uint status = dma->sr;
 
 	/* While the channel is busy, spin */
 	while((status & 4) == 4) {
-		status = dma->sr0;
+		status = dma->sr;
 	}
 
-	/* clear MR0[CS] channel start bit */
-	dma->mr0 &= 0x00000001;
+	/* clear MR[CS] channel start bit */
+	dma->mr &= 0x00000001;
 	asm("sync;isync;msync");
 
 	if (status != 0) {
@@ -289,14 +297,15 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->dar0 = (uint) dest;
-	dma->sar0 = (uint) src;
-	dma->bcr0 = count;
-	dma->mr0 = 0xf000004;
+	dma->dar = (uint) dest;
+	dma->sar = (uint) src;
+	dma->bcr = count;
+	dma->mr = 0xf000004;
 	asm("sync;isync;msync");
-	dma->mr0 = 0xf000005;
+	dma->mr = 0xf000005;
 	asm("sync;isync;msync");
 	return dma_check();
 }
@@ -377,24 +386,11 @@ int cpu_eth_init(bd_t *bis)
 #if defined(CONFIG_ETHER_ON_FCC)
 	fec_initialize(bis);
 #endif
-#if defined(CONFIG_UEC_ETH1)
-	uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
-	uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
-	uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
-	uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
-	uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
-	uec_initialize(5);
+
+#if defined(CONFIG_UEC_ETH)
+	uec_standard_init(bis);
 #endif
+
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
 	tsec_standard_init(bis);
 #endif
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 26a8f48..a692529 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -278,12 +278,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	if (!IS_E_PROCESSOR(get_svr()))
 		fdt_fixup_crypto_node(blob, 0);
 
-#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
-    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 	fdt_fixup_ethernet(blob);
 
 	fdt_add_enet_stashing(blob);
-#endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"timebase-frequency", bd->bi_busfreq / 8, 1);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index b0f47e0..286b6b2 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
  *
@@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
 	uint plat_ratio,e500_ratio,half_freqSystemBus;
 	uint lcrr_div;
 	int i;
+#ifdef CONFIG_QE
+	u32 qe_ratio;
+#endif
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
@@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
 	}
 #endif
 
+#ifdef CONFIG_QE
+	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
+			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+#endif
+
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -112,6 +121,10 @@ int get_clocks (void)
 	gd->mem_clk = sys_info.freqDDRBus;
 	gd->lbc_clk = sys_info.freqLocalBus;
 
+#ifdef CONFIG_QE
+	gd->qe_clk = sys_info.freqQE;
+	gd->brg_clk = gd->qe_clk / 2;
+#endif
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
 	 * there is no pattern that can be used to determine the frequency, so
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 653a137..d47cc5e 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -182,26 +182,31 @@ watchdog_reset(void)
 void
 dma_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr0 = 0x00040000;
-	dma->datr0 = 0x00040000;
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync");
 }
 
 uint
 dma_check(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
-	volatile uint status = dma->sr0;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
+	volatile uint status = dma->sr;
 
 	/* While the channel is busy, spin */
 	while ((status & 4) == 4) {
-		status = dma->sr0;
+		status = dma->sr;
 	}
 
+	/* clear MR[CS] channel start bit */
+	dma->mr &= 0x00000001;
+	asm("sync;isync");
+
 	if (status != 0) {
 		printf("DMA Error: status = %x\n", status);
 	}
@@ -211,15 +216,15 @@ dma_check(void)
 int
 dma_xfer(void *dest, uint count, void *src)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->dar0 = (uint) dest;
-	dma->sar0 = (uint) src;
-	dma->bcr0 = count;
-	dma->mr0 = 0xf000004;
+	dma->dar = (uint) dest;
+	dma->sar = (uint) src;
+	dma->bcr = count;
+	dma->mr = 0xf000004;
 	asm("sync;isync");
-	dma->mr0 = 0xf000005;
+	dma->mr = 0xf000005;
 	asm("sync;isync");
 	return dma_check();
 }
diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c
index 2c2e838..33553b7 100644
--- a/cpu/nios/asmi.c
+++ b/cpu/nios/asmi.c
@@ -48,7 +48,7 @@
 	"asmi write addr offset count\n"\
 	"    - write count bytes to offset from addr.\n"\
 	"asmi verify addr offset count\n"\
-	"    - verify count bytes at offset from addr.\n"
+	"    - verify count bytes at offset from addr."
 
 
 /*-----------------------------------------------------------------------*/
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index 968b50f..483b249 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -47,7 +47,7 @@
 	"epcs write addr offset count\n"\
 	"    - write count bytes to offset from addr.\n"\
 	"epcs verify addr offset count\n"\
-	"    - verify count bytes at offset from addr.\n"
+	"    - verify count bytes at offset from addr."
 
 
 /*-----------------------------------------------------------------------*/
diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c
index 251204b..77bc8b5 100644
--- a/cpu/nios2/sysid.c
+++ b/cpu/nios2/sysid.c
@@ -53,6 +53,6 @@ int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
 	sysid,	1,	1,	do_sysid,
 	"display Nios-II system id",
-	"\n    - display Nios-II system id\n"
+	""
 );
 #endif /* CONFIG_SYS_NIOS_SYSID_BASE */
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index 57861b3..75bd70d 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -56,10 +56,6 @@
 #define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CONFIG_SYS_I2C_SLAVE
-#define CONFIG_SYS_I2C_SLAVE	0xFE
-#endif
-
 #define ONE_BILLION	1000000000
 
 #define	 SDRAM0_CFG_DCE		0x80000000
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index 153391e..f26fcda 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -66,10 +66,6 @@
 #define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CONFIG_SYS_I2C_SLAVE
-#define CONFIG_SYS_I2C_SLAVE	0xFE
-#endif
-
 #define ONE_BILLION	1000000000
 
 /*
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 9a6a8d7..06f44ad 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -597,7 +597,7 @@ int checkcpu (void)
 	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 #endif
 
-#if defined(PCI_ASYNC)
+#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
 	if (pci_async_enabled()) {
 		printf (", PCI async ext clock used");
 	} else {
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 9d416ca..e3e1bab 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -438,18 +438,4 @@ int i2c_set_bus_num(unsigned int bus)
 	return 0;
 }
 #endif	/* CONFIG_I2C_MULTI_BUS */
-
-/* TODO: add 100/400k switching */
-unsigned int i2c_get_bus_speed(void)
-{
-	return CONFIG_SYS_I2C_SPEED;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
-	if (speed != CONFIG_SYS_I2C_SPEED)
-		return -1;
-
-	return 0;
-}
 #endif	/* CONFIG_HARD_I2C */
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index f2b8908..ac96fc2 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -257,6 +257,14 @@
 	bl	board_init_f
 #endif
 
+#if defined(CONFIG_SYS_RAMBOOT)
+	/*
+	 * 4xx RAM-booting U-Boot image is started from offset 0
+	 */
+	.text
+	bl	_start_440
+#endif
+
 /*
  * 440 Startup -- on reset only the top 4k of the effective
  * address space is mapped in by an entry in the instruction
@@ -444,10 +452,17 @@ skip_debug_init:
 	addis	r0,0,0x0000
 	li	r1,0x003f	/* 64 TLB entries */
 	mtctr	r1
-rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
-	tlbwe	r0,r1,0x0001
-	tlbwe	r0,r1,0x0002
-	subi	r1,r1,0x0001
+	li	r4,0		/* Start with TLB #0 */
+rsttlb:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 to get EPN */
+	rlwinm.	r3,r3,0,0xfffffc00	/* Mask EPN */
+	beq	tlbnxt		/* Skip EPN=0 TLB, this is the SDRAM TLB */
+#endif
+	tlbwe	r0,r4,0		/* Invalidate all entries (V=0)*/
+	tlbwe	r0,r4,1
+	tlbwe	r0,r4,2
+tlbnxt:	addi	r4,r4,1		/* Next TLB */
 	bdnz	rsttlb
 
 	/*----------------------------------------------------------------*/
@@ -476,7 +491,13 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	li	r4,0		/* TLB # */
 
 	addi	r5,r5,-4
-1:	lwzu	r0,4(r5)
+1:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 */
+	rlwinm.	r3,r3,0,0x00000200	/* Mask V (valid) bit */
+	bne	tlbnx2		/* Skip V=1 TLB, this is the SDRAM TLB */
+#endif
+	lwzu	r0,4(r5)
 	cmpwi	r0,0
 	beq	2f		/* 0 marks end */
 	lwzu	r1,4(r5)
@@ -484,7 +505,7 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	tlbwe	r0,r4,0		/* TLB Word 0 */
 	tlbwe	r1,r4,1		/* TLB Word 1 */
 	tlbwe	r2,r4,2		/* TLB Word 2 */
-	addi	r4,r4,1		/* Next TLB */
+tlbnx2:	addi	r4,r4,1		/* Next TLB */
 	bdnz	1b
 
 	/*----------------------------------------------------------------*/
diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile
index 42903b2..07a151a 100644
--- a/cpu/pxa/Makefile
+++ b/cpu/pxa/Makefile
@@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= serial.o interrupts.o cpu.o i2c.o pxafb.o usb.o
+
+COBJS	+= cpu.o
+COBJS	+= i2c.o
+COBJS	+= pxafb.o
+COBJS	+= timer.o
+COBJS	+= usb.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index 3a1be57..800d120 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -35,24 +35,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
deleted file mode 100644
index 9ba457e..0000000
--- a/cpu/pxa/serial.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FFUART_INDEX	0
-#define BTUART_INDEX	1
-#define STUART_INDEX	2
-
-#ifndef CONFIG_SERIAL_MULTI
-#if defined (CONFIG_FFUART)
-#define UART_INDEX	FFUART_INDEX
-#elif defined (CONFIG_BTUART)
-#define UART_INDEX	BTUART_INDEX
-#elif defined (CONFIG_STUART)
-#define UART_INDEX	STUART_INDEX
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-#endif
-
-void pxa_setbrg_dev (unsigned int uart_index)
-{
-	unsigned int quot = 0;
-
-	if (gd->baudrate == 1200)
-		quot = 768;
-	else if (gd->baudrate == 9600)
-		quot = 96;
-	else if (gd->baudrate == 19200)
-		quot = 48;
-	else if (gd->baudrate == 38400)
-		quot = 24;
-	else if (gd->baudrate == 57600)
-		quot = 16;
-	else if (gd->baudrate == 115200)
-		quot = 8;
-	else
-		hang ();
-
-	switch (uart_index) {
-		case FFUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_22_FFUART;
-#else
-			CKEN |= CKEN6_FFUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-			FFIER = 0;	/* Disable for now */
-			FFFCR = 0;	/* No fifos enabled */
-
-			/* set baud rate */
-			FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-			FFDLL = quot & 0xff;
-			FFDLH = quot >> 8;
-			FFLCR = LCR_WLS0 | LCR_WLS1;
-
-			FFIER = IER_UUE;	/* Enable FFUART */
-		break;
-
-		case BTUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_21_BTUART;
-#else
-			CKEN |= CKEN7_BTUART;
-#endif /*  CONFIG_CPU_MONAHANS */
-
-			BTIER = 0;
-			BTFCR = 0;
-
-			/* set baud rate */
-			BTLCR = LCR_DLAB;
-			BTDLL = quot & 0xff;
-			BTDLH = quot >> 8;
-			BTLCR = LCR_WLS0 | LCR_WLS1;
-
-			BTIER = IER_UUE;	/* Enable BFUART */
-
-		break;
-
-		case STUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_23_STUART;
-#else
-			CKEN |= CKEN5_STUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-			STIER = 0;
-			STFCR = 0;
-
-			/* set baud rate */
-			STLCR = LCR_DLAB;
-			STDLL = quot & 0xff;
-			STDLH = quot >> 8;
-			STLCR = LCR_WLS0 | LCR_WLS1;
-
-			STIER = IER_UUE;			/* Enable STUART */
-			break;
-
-		default:
-			hang();
-	}
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int pxa_init_dev (unsigned int uart_index)
-{
-	pxa_setbrg_dev (uart_index);
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void pxa_putc_dev (unsigned int uart_index,const char c)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-		/* wait for room in the tx FIFO on FFUART */
-			while ((FFLSR & LSR_TEMT) == 0)
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			FFTHR = c;
-			break;
-
-		case BTUART_INDEX:
-			while ((BTLSR & LSR_TEMT ) == 0 )
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			BTTHR = c;
-			break;
-
-		case STUART_INDEX:
-			while ((STLSR & LSR_TEMT ) == 0 )
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			STTHR = c;
-			break;
-	}
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		pxa_putc_dev (uart_index,'\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_tstc_dev (unsigned int uart_index)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-			return FFLSR & LSR_DR;
-		case BTUART_INDEX:
-			return BTLSR & LSR_DR;
-		case STUART_INDEX:
-			return STLSR & LSR_DR;
-	}
-	return -1;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_getc_dev (unsigned int uart_index)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-			while (!(FFLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) FFRBR & 0xff;
-
-		case BTUART_INDEX:
-			while (!(BTLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) BTRBR & 0xff;
-		case STUART_INDEX:
-			while (!(STLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) STRBR & 0xff;
-	}
-	return -1;
-}
-
-void
-pxa_puts_dev (unsigned int uart_index,const char *s)
-{
-	while (*s) {
-		pxa_putc_dev (uart_index,*s++);
-	}
-}
-
-#if defined (CONFIG_FFUART)
-static int ffuart_init(void)
-{
-	return pxa_init_dev(FFUART_INDEX);
-}
-
-static void ffuart_setbrg(void)
-{
-	return pxa_setbrg_dev(FFUART_INDEX);
-}
-
-static void ffuart_putc(const char c)
-{
-	return pxa_putc_dev(FFUART_INDEX,c);
-}
-
-static void ffuart_puts(const char *s)
-{
-	return pxa_puts_dev(FFUART_INDEX,s);
-}
-
-static int ffuart_getc(void)
-{
-	return pxa_getc_dev(FFUART_INDEX);
-}
-
-static int ffuart_tstc(void)
-{
-	return pxa_tstc_dev(FFUART_INDEX);
-}
-
-struct serial_device serial_ffuart_device =
-{
-	"serial_ffuart",
-	"PXA",
-	ffuart_init,
-	ffuart_setbrg,
-	ffuart_getc,
-	ffuart_tstc,
-	ffuart_putc,
-	ffuart_puts,
-};
-#endif
-
-#if defined (CONFIG_BTUART)
-static int btuart_init(void)
-{
-	return pxa_init_dev(BTUART_INDEX);
-}
-
-static void btuart_setbrg(void)
-{
-	return pxa_setbrg_dev(BTUART_INDEX);
-}
-
-static void btuart_putc(const char c)
-{
-	return pxa_putc_dev(BTUART_INDEX,c);
-}
-
-static void btuart_puts(const char *s)
-{
-	return pxa_puts_dev(BTUART_INDEX,s);
-}
-
-static int btuart_getc(void)
-{
-	return pxa_getc_dev(BTUART_INDEX);
-}
-
-static int btuart_tstc(void)
-{
-	return pxa_tstc_dev(BTUART_INDEX);
-}
-
-struct serial_device serial_btuart_device =
-{
-	"serial_btuart",
-	"PXA",
-	btuart_init,
-	btuart_setbrg,
-	btuart_getc,
-	btuart_tstc,
-	btuart_putc,
-	btuart_puts,
-};
-#endif
-
-#if defined (CONFIG_STUART)
-static int stuart_init(void)
-{
-	return pxa_init_dev(STUART_INDEX);
-}
-
-static void stuart_setbrg(void)
-{
-	return pxa_setbrg_dev(STUART_INDEX);
-}
-
-static void stuart_putc(const char c)
-{
-	return pxa_putc_dev(STUART_INDEX,c);
-}
-
-static void stuart_puts(const char *s)
-{
-	return pxa_puts_dev(STUART_INDEX,s);
-}
-
-static int stuart_getc(void)
-{
-	return pxa_getc_dev(STUART_INDEX);
-}
-
-static int stuart_tstc(void)
-{
-	return pxa_tstc_dev(STUART_INDEX);
-}
-
-struct serial_device serial_stuart_device =
-{
-	"serial_stuart",
-	"PXA",
-	stuart_init,
-	stuart_setbrg,
-	stuart_getc,
-	stuart_tstc,
-	stuart_putc,
-	stuart_puts,
-};
-#endif
-
-
-#ifndef CONFIG_SERIAL_MULTI
-inline int serial_init(void) {
-	return (pxa_init_dev(UART_INDEX));
-}
-void serial_setbrg(void) {
-	pxa_setbrg_dev(UART_INDEX);
-}
-int serial_getc(void) {
-	return(pxa_getc_dev(UART_INDEX));
-}
-int serial_tstc(void) {
-	return(pxa_tstc_dev(UART_INDEX));
-}
-void serial_putc(const char c) {
-	pxa_putc_dev(UART_INDEX,c);
-}
-void serial_puts(const char *s) {
-	pxa_puts_dev(UART_INDEX,s);
-}
-#endif	/* CONFIG_SERIAL_MULTI */
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/timer.c
index 2bc5c50..e2df3a5 100644
--- a/cpu/pxa/interrupts.c
+++ b/cpu/pxa/timer.c
@@ -56,10 +56,11 @@ static inline unsigned long long us_to_tick(unsigned long long us)
 	return us;
 }
 
-int interrupt_init (void)
+int timer_init (void)
 {
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
+	reset_timer();
+
+	return 0;
 }
 
 void reset_timer (void)
diff --git a/cpu/pxa/u-boot.lds b/cpu/pxa/u-boot.lds
new file mode 100644
index 0000000..77ab3c9
--- /dev/null
+++ b/cpu/pxa/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/pxa/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile
index ae909a6..6da2016 100644
--- a/cpu/s3c44b0/Makefile
+++ b/cpu/s3c44b0/Makefile
@@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cache.o cpu.o interrupts.o
+
+COBJS	+= cache.o
+COBJS	+= cpu.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c
index 7ef4a1f..bca38f8 100644
--- a/cpu/s3c44b0/cpu.c
+++ b/cpu/s3c44b0/cpu.c
@@ -32,7 +32,7 @@
 #include <command.h>
 #include <asm/hardware.h>
 
-int cpu_init (void)
+int arch_cpu_init (void)
 {
 	icache_enable();
 
diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/timer.c
index eb23e6a..34184ab 100644
--- a/cpu/s3c44b0/interrupts.c
+++ b/cpu/s3c44b0/timer.c
@@ -40,7 +40,7 @@
 static ulong timestamp;
 static ulong lastdec;
 
-int interrupt_init (void)
+int timer_init (void)
 {
 	TCFG0 = 0x000000E9;
 	TCFG1 = 0x00000004;
diff --git a/cpu/s3c44b0/u-boot.lds b/cpu/s3c44b0/u-boot.lds
new file mode 100644
index 0000000..41ca3b4
--- /dev/null
+++ b/cpu/s3c44b0/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/s3c44b0/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile
index fd696f7..28b6682 100644
--- a/cpu/sa1100/Makefile
+++ b/cpu/sa1100/Makefile
@@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o
+
+COBJS	+= cpu.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index ed1a6f7..58e90dc 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -40,18 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/timer.c
index 2eff045..3f77e81 100644
--- a/cpu/sa1100/interrupts.c
+++ b/cpu/sa1100/timer.c
@@ -29,10 +29,9 @@
 #include <common.h>
 #include <SA-1100.h>
 
-int interrupt_init (void)
+int timer_init (void)
 {
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
+	return 0;
 }
 
 void reset_timer (void)
diff --git a/cpu/sa1100/u-boot.lds b/cpu/sa1100/u-boot.lds
new file mode 100644
index 0000000..0c02e76
--- /dev/null
+++ b/cpu/sa1100/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003-2004
+ * MontaVista Software, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}