From 9c90a2c8e87414007a016b7cd099ac1e32fd301b Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 24 Apr 2009 15:34:05 -0500 Subject: i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE value Many boards/controllers/drivers don't support an I2C slave interface, however CONFIG_SYS_I2C_SLAVE is used in common code so provide a default Signed-off-by: Peter Tyser --- cpu/mpc8260/i2c.c | 3 --- cpu/ppc4xx/40x_spd_sdram.c | 4 ---- cpu/ppc4xx/44x_spd_ddr.c | 4 ---- 3 files changed, 11 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index 35cf8f1..2b954b4 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -58,9 +58,6 @@ static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; #define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xFE -#endif /*----------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 57861b3..75bd70d 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -56,10 +56,6 @@ #define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xFE -#endif - #define ONE_BILLION 1000000000 #define SDRAM0_CFG_DCE 0x80000000 diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 153391e..f26fcda 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -66,10 +66,6 @@ #define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xFE -#endif - #define ONE_BILLION 1000000000 /* -- cgit v1.1 From 655b34a78adf60ef260981688837904208883ae9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Sat, 18 Apr 2009 22:34:01 -0500 Subject: i2c: Create common default i2c_[set|get]_bus_speed() functions New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions replace a number of architecture-specific implementations. Also, providing default functions will allow all boards to enable CONFIG_I2C_CMD_TREE. This was previously not possible since the tree-form of the i2c command provides the ability to display and modify the i2c bus speed which requires i2c_[set|get]_bus_speed() to be present. Signed-off-by: Peter Tyser --- cpu/arm920t/at91rm9200/i2c.c | 10 ---------- cpu/mpc512x/i2c.c | 14 -------------- cpu/mpc8260/i2c.c | 13 ------------- cpu/ppc4xx/i2c.c | 14 -------------- 4 files changed, 51 deletions(-) (limited to 'cpu') diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c index 9fd72d3..1711088 100644 --- a/cpu/arm920t/at91rm9200/i2c.c +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -189,14 +189,4 @@ i2c_init(int speed, int slaveaddr) return; } -int i2c_set_bus_speed(unsigned int speed) -{ - return -1; -} - -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 4f6bc86..0da906a 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -397,18 +397,4 @@ unsigned int i2c_get_bus_num (void) return bus_num; } -/* TODO */ -unsigned int i2c_get_bus_speed (void) -{ - return -1; -} - -int i2c_set_bus_speed (unsigned int speed) -{ - if (speed != CONFIG_SYS_I2C_SPEED) - return -1; - - return 0; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index 2b954b4..d2bdcc2 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -780,19 +780,6 @@ int i2c_set_bus_num(unsigned int bus) #endif return 0; } -/* TODO: add 100/400k switching */ -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - if (speed != CONFIG_SYS_I2C_SPEED) - return -1; - - return 0; -} #endif /* CONFIG_I2C_MULTI_BUS */ #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 9d416ca..e3e1bab 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -438,18 +438,4 @@ int i2c_set_bus_num(unsigned int bus) return 0; } #endif /* CONFIG_I2C_MULTI_BUS */ - -/* TODO: add 100/400k switching */ -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - if (speed != CONFIG_SYS_I2C_SPEED) - return -1; - - return 0; -} #endif /* CONFIG_HARD_I2C */ -- cgit v1.1 From d873133f2ba9bd613d5f6552c31cc70fb13f15d3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 11 May 2009 13:46:14 +0200 Subject: ppc4xx: Add Sequoia RAM-booting target This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese --- cpu/ppc4xx/start.S | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f2b8908..ac96fc2 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -257,6 +257,14 @@ bl board_init_f #endif +#if defined(CONFIG_SYS_RAMBOOT) + /* + * 4xx RAM-booting U-Boot image is started from offset 0 + */ + .text + bl _start_440 +#endif + /* * 440 Startup -- on reset only the top 4k of the effective * address space is mapped in by an entry in the instruction @@ -444,10 +452,17 @@ skip_debug_init: addis r0,0,0x0000 li r1,0x003f /* 64 TLB entries */ mtctr r1 -rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ - tlbwe r0,r1,0x0001 - tlbwe r0,r1,0x0002 - subi r1,r1,0x0001 + li r4,0 /* Start with TLB #0 */ +rsttlb: +#ifdef CONFIG_SYS_RAMBOOT + tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ + rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ + beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ +#endif + tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ + tlbwe r0,r4,1 + tlbwe r0,r4,2 +tlbnxt: addi r4,r4,1 /* Next TLB */ bdnz rsttlb /*----------------------------------------------------------------*/ @@ -476,7 +491,13 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ li r4,0 /* TLB # */ addi r5,r5,-4 -1: lwzu r0,4(r5) +1: +#ifdef CONFIG_SYS_RAMBOOT + tlbre r3,r4,0 /* Read contents from TLB word #0 */ + rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ + bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ +#endif + lwzu r0,4(r5) cmpwi r0,0 beq 2f /* 0 marks end */ lwzu r1,4(r5) @@ -484,7 +505,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ tlbwe r0,r4,0 /* TLB Word 0 */ tlbwe r1,r4,1 /* TLB Word 1 */ tlbwe r2,r4,2 /* TLB Word 2 */ - addi r4,r4,1 /* Next TLB */ +tlbnx2: addi r4,r4,1 /* Next TLB */ bdnz 1b /*----------------------------------------------------------------*/ -- cgit v1.1 From 84f7411cb901b8df2391cf7e967ad0737f6194aa Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 14 Apr 2009 08:52:58 -0700 Subject: DaVinci now respects SKIP_LOWLEVEL_INIT Don't needlessly include lowlevel init code; that's only really needed with boot-from NOR (not boot-from-NAND). The 2nd stage loader (UBL) handles that before it loads U-Boot. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index ed24e65..7f51d17 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -28,7 +28,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS = timer.o ether.o lxt972.o dp83848.o -SOBJS = lowlevel_init.o reset.o +SOBJS = reset.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS += lowlevel_init.o +endif SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -- cgit v1.1 From 7b7808ae6dace59287f565e9323cda7b098a5612 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:44:06 +0200 Subject: davinci: move psc support board-->cpu Move DaVinci PSC support from board/* to cpu/* where it belongs. The PSC module manages clocks and resets for all DaVinci-family SoCs, and isn't at all board-specific. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 2 +- cpu/arm926ejs/davinci/psc.c | 182 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 cpu/arm926ejs/davinci/psc.c (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 7f51d17..83708d8 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o ether.o lxt972.o dp83848.o +COBJS = timer.o ether.o lxt972.o dp83848.o psc.o SOBJS = reset.o ifndef CONFIG_SKIP_LOWLEVEL_INIT diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c new file mode 100644 index 0000000..28e2a4b --- /dev/null +++ b/cpu/arm926ejs/davinci/psc.c @@ -0,0 +1,182 @@ +/* + * Power and Sleep Controller (PSC) functions. + * + * Copyright (C) 2007 Sergey Kubushyn + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#define PINMUX0_EMACEN (1 << 31) +#define PINMUX0_AECS5 (1 << 11) +#define PINMUX0_AECS4 (1 << 10) + +#define PINMUX1_I2C (1 << 7) +#define PINMUX1_UART1 (1 << 1) +#define PINMUX1_UART0 (1 << 0) + +/* + * The DM6446 includes two separate power domains: "Always On" and "DSP". The + * "Always On" power domain is always on when the chip is on. The "Always On" + * domain is powered by the VDD pins of the DM6446. The majority of the + * DM6446's modules lie within the "Always On" power domain. A separate + * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain + * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of + * the DM6446. + */ + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01); + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + switch (id) { + case DAVINCI_LPSC_VPSSSLV: + case DAVINCI_LPSC_EMAC: + case DAVINCI_LPSC_EMAC_WRAPPER: + case DAVINCI_LPSC_MDIO: + case DAVINCI_LPSC_USB: + case DAVINCI_LPSC_ATA: + case DAVINCI_LPSC_VLYNQ: + case DAVINCI_LPSC_UHPI: + case DAVINCI_LPSC_DDR_EMIF: + case DAVINCI_LPSC_AEMIF: + case DAVINCI_LPSC_MMC_SD: + case DAVINCI_LPSC_MEMSTICK: + case DAVINCI_LPSC_McBSP: + case DAVINCI_LPSC_GPIO: + *mdctl |= 0x200; + break; + } + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03); + while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ +} + +/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ +#if !defined(CONFIG_SYS_USE_DSPLINK) +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} +#endif /* CONFIG_SYS_USE_DSPLINK */ + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= PINMUX1_UART0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +void davinci_enable_emac(void) +{ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable EMAC. */ + REG(PINMUX0) |= PINMUX0_EMACEN; +} +#endif + +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= PINMUX1_I2C; +} + +void davinci_errata_workarounds(void) +{ + /* + * Workaround for TMS320DM6446 errata 1.3.22: + * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset + * Revision(s) Affected: 1.3 and earlier + */ + REG(PSC_SILVER_BULLET) = 0; + + /* + * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) + * as suggested in TMS320DM6446 errata 2.1.2: + * + * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions + * low priority modules can occupy the bus and prevent high priority + * modules like the VPSS from getting the required DDR2 throughput. + * A hex value of 0x20 should provide a good ARM (cache enabled) + * performance and still allow good utilization by the VPSS or other + * modules. + */ + REG(VBPR) = 0x20; +} -- cgit v1.1 From 48ef5729555f41f51618b6a3016ac5c53c7c75dc Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:44:08 +0200 Subject: davinci: cpu-specific build uses conditional make syntax Update cpu/arm926ejs/davinci/Makefile to use COBJ-y type syntax. Add the first conditional: for EMAC driver support. Not all chips have an EMAC; and boards might not use it, anyway. This doesn't touch PHY configuration; that should eventually become conditional too. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 83708d8..e09874b 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,15 +27,17 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o ether.o lxt972.o dp83848.o psc.o +COBJS-y += timer.o psc.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o + SOBJS = reset.o ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS += lowlevel_init.o endif -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(LIB) -- cgit v1.1 From f79043681ff44bae435c06f830e51e1546db7e19 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:44:08 +0200 Subject: davinci: split out some dm644x-specific bits from psc Split out DaVinci DM6446-specific bits from more generic bits: - Add a CONFIG_SOC_DM644X. All current boards use DM6446 chips; DM6443 and DM6441 chips differ in available peripherals. - Move most DM644X-specific bits from psc.c to a new dm644x.c file, which is conditionally built. It provides device-specific setup. Plus minor coding style and comment updates with respect to the PSC. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 1 + cpu/arm926ejs/davinci/dm644x.c | 94 +++++++++++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/psc.c | 103 +++++++++++------------------------------ 3 files changed, 123 insertions(+), 75 deletions(-) create mode 100644 cpu/arm926ejs/davinci/dm644x.c (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index e09874b..6052e02 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS-y += timer.o psc.o +COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o SOBJS = reset.o diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c new file mode 100644 index 0000000..df382bd --- /dev/null +++ b/cpu/arm926ejs/davinci/dm644x.c @@ -0,0 +1,94 @@ +/* + * SoC-specific code for tms320dm644x chips + * + * Copyright (C) 2007 Sergey Kubushyn + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + + +#define PINMUX0_EMACEN (1 << 31) +#define PINMUX0_AECS5 (1 << 11) +#define PINMUX0_AECS4 (1 << 10) + +#define PINMUX1_I2C (1 << 7) +#define PINMUX1_UART1 (1 << 1) +#define PINMUX1_UART0 (1 << 0) + + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= PINMUX1_UART0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +void davinci_enable_emac(void) +{ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable EMAC. */ + REG(PINMUX0) |= PINMUX0_EMACEN; +} +#endif + +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= PINMUX1_I2C; +} + +void davinci_errata_workarounds(void) +{ + /* + * Workaround for TMS320DM6446 errata 1.3.22: + * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset + * Revision(s) Affected: 1.3 and earlier + */ + REG(PSC_SILVER_BULLET) = 0; + + /* + * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) + * as suggested in TMS320DM6446 errata 2.1.2: + * + * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions + * low priority modules can occupy the bus and prevent high priority + * modules like the VPSS from getting the required DDR2 throughput. + * A hex value of 0x20 should provide a good ARM (cache enabled) + * performance and still allow good utilization by the VPSS or other + * modules. + */ + REG(VBPR) = 0x20; +} diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c index 28e2a4b..5bb972f 100644 --- a/cpu/arm926ejs/davinci/psc.c +++ b/cpu/arm926ejs/davinci/psc.c @@ -26,22 +26,22 @@ #include #include -#define PINMUX0_EMACEN (1 << 31) -#define PINMUX0_AECS5 (1 << 11) -#define PINMUX0_AECS4 (1 << 10) - -#define PINMUX1_I2C (1 << 7) -#define PINMUX1_UART1 (1 << 1) -#define PINMUX1_UART0 (1 << 0) - /* - * The DM6446 includes two separate power domains: "Always On" and "DSP". The - * "Always On" power domain is always on when the chip is on. The "Always On" - * domain is powered by the VDD pins of the DM6446. The majority of the - * DM6446's modules lie within the "Always On" power domain. A separate - * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain - * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of - * the DM6446. + * The PSC manages three inputs to a "module" which may be a peripheral or + * CPU. Those inputs are the module's: clock; reset signal; and sometimes + * its power domain. For our purposes, we only care whether clock and power + * are active, and the module is out of reset. + * + * DaVinci chips may include two separate power domains: "Always On" and "DSP". + * Chips without a DSP generally have only one domain. + * + * The "Always On" power domain is always on when the chip is on, and is + * powered by the VDD pins (on DM644X). The majority of DaVinci modules + * lie within the "Always On" power domain. + * + * A separate domain called the "DSP" domain houses the C64x+ and other video + * hardware such as VICP. In some chips, the "DSP" domain is not always on. + * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X). */ /* Works on Always On power domain only (no PD argument) */ @@ -55,15 +55,17 @@ void lpsc_on(unsigned int id) mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - while (REG(PSC_PTSTAT) & 0x01); + while (REG(PSC_PTSTAT) & 0x01) + continue; if ((*mdstat & 0x1f) == 0x03) return; /* Already on and enabled */ *mdctl |= 0x03; - /* Special treatment for some modules as for sprue14 p.7.4.2 */ switch (id) { +#ifdef CONFIG_SOC_DM644X + /* Special treatment for some modules as for sprue14 p.7.4.2 */ case DAVINCI_LPSC_VPSSSLV: case DAVINCI_LPSC_EMAC: case DAVINCI_LPSC_EMAC_WRAPPER: @@ -80,14 +82,20 @@ void lpsc_on(unsigned int id) case DAVINCI_LPSC_GPIO: *mdctl |= 0x200; break; +#endif } REG(PSC_PTCMD) = 0x01; - while (REG(PSC_PTSTAT) & 0x03); - while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ + while (REG(PSC_PTSTAT) & 0x03) + continue; + while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */ + continue; } +/* Not all DaVinci chips have a DSP power domain. */ +#ifdef CONFIG_SOC_DM644X + /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ #if !defined(CONFIG_SYS_USE_DSPLINK) void dsp_on(void) @@ -124,59 +132,4 @@ void dsp_on(void) } #endif /* CONFIG_SYS_USE_DSPLINK */ -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= PINMUX1_UART0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable EMAC. */ - REG(PINMUX0) |= PINMUX0_EMACEN; -} -#endif - -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= PINMUX1_I2C; -} - -void davinci_errata_workarounds(void) -{ - /* - * Workaround for TMS320DM6446 errata 1.3.22: - * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset - * Revision(s) Affected: 1.3 and earlier - */ - REG(PSC_SILVER_BULLET) = 0; - - /* - * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) - * as suggested in TMS320DM6446 errata 2.1.2: - * - * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions - * low priority modules can occupy the bus and prevent high priority - * modules like the VPSS from getting the required DDR2 throughput. - * A hex value of 0x20 should provide a good ARM (cache enabled) - * performance and still allow good utilization by the VPSS or other - * modules. - */ - REG(VBPR) = 0x20; -} +#endif /* have a DSP */ -- cgit v1.1 From bd36fdc146654f9de4e2ad346126e6bd2990fb19 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:44:09 +0200 Subject: davinci: fix dm644x buglets Fix two buglets in the dm644x support: don't set two must-be-zero bits in the UART management register; and only include the I2C hooks if the I2C driver is being included. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/dm644x.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c index df382bd..bb105b5 100644 --- a/cpu/arm926ejs/davinci/dm644x.c +++ b/cpu/arm926ejs/davinci/dm644x.c @@ -41,7 +41,7 @@ void davinci_enable_uart0(void) lpsc_on(DAVINCI_LPSC_UART0); /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; + REG(UART0_PWREMU_MGMT) = 0x00006001; /* Enable UART0 MUX lines */ REG(PINMUX1) |= PINMUX1_UART0; @@ -62,6 +62,7 @@ void davinci_enable_emac(void) } #endif +#ifdef CONFIG_DRIVER_DAVINCI_I2C void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); @@ -69,6 +70,7 @@ void davinci_enable_i2c(void) /* Enable I2C pin Mux */ REG(PINMUX1) |= PINMUX1_I2C; } +#endif void davinci_errata_workarounds(void) { -- cgit v1.1 From f1d944e30eb8ff89080fa03fb98d8fb5c82388d2 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:44:09 +0200 Subject: davinci: add basic dm355/dm350/dm335 support Add some basic declarations for DaVinci DM355/DM350/DM335 support, keyed on CONFIG_SOC_DM355. (DM35X isn't quite right because the DM357 is very different; while the DM355 is like a DM355 without the MPEG/JPEG coprocessor). These have different peripherals than the DM6446, and some of the peripherals are at different addresses. Notably for U-Boot, there's no EMAC, and the NAND controller address is different Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 1 + cpu/arm926ejs/davinci/dm355.c | 45 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 cpu/arm926ejs/davinci/dm355.c (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 6052e02..480f19f 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS-y += timer.o psc.o +COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c new file mode 100644 index 0000000..bc45b67 --- /dev/null +++ b/cpu/arm926ejs/davinci/dm355.c @@ -0,0 +1,45 @@ +/* + * SoC-specific code for tms320dm355 and similar chips + * + * Copyright (C) 2009 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x00006001; +} + + +#ifdef CONFIG_DRIVER_DAVINCI_I2C +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); + + /* Enable I2C pin Mux */ + REG(PINMUX3) |= (1 << 20) | (1 << 19); +} +#endif -- cgit v1.1 From c20e28f49aaf38c7dede46d8f8fe8234fe90822c Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:12 +0200 Subject: arm946es: remove non used timer Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm946es/Makefile | 3 +- cpu/arm946es/interrupts.c | 158 ---------------------------------------------- 2 files changed, 2 insertions(+), 159 deletions(-) delete mode 100644 cpu/arm946es/interrupts.c (limited to 'cpu') diff --git a/cpu/arm946es/Makefile b/cpu/arm946es/Makefile index d5ac7d3..e81f2da 100644 --- a/cpu/arm946es/Makefile +++ b/cpu/arm946es/Makefile @@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o + +COBJS = cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c deleted file mode 100644 index 3a16abe..0000000 --- a/cpu/arm946es/interrupts.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define TIMER_LOAD_VAL 0xffffffff -extern void reset_cpu(ulong addr); - -#ifdef CONFIG_INTEGRATOR - /* Timer functionality supplied by Integrator board (AP or CP) */ -#else - -static ulong timestamp; -static ulong lastdec; - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND perserve advance timstamp value */ -void udelay(unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_raw (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ - } else { /* we have overflow of the count down timer */ - /* nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -ulong get_timer_masked (void) -{ - return get_timer_raw() / TIMER_LOAD_VAL; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ_CLOCK; - tmo /= (1000*1000); - } - - reset_timer_masked (); /* set "advancing" timestamp to 0, set lastdec vaule */ - - while (get_timer_raw () < tmo) /* wait for time stamp to overtake tick number.*/ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} - -#endif /* CONFIG_INTEGRATOR */ -- cgit v1.1 From 8fc3bb4b0603516ad641e2de252a400b85fd869b Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:20 +0200 Subject: arm: cleanup remaining CONFIG_INIT_CRITICAL Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm946es/start.S | 4 +++- cpu/arm_intcm/start.S | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S index 9375c76..627e3cb 100644 --- a/cpu/arm946es/start.S +++ b/cpu/arm946es/start.S @@ -133,7 +133,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifdef CONFIG_INIT_CRITICAL +#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif @@ -192,6 +192,7 @@ _start_armboot: */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -217,6 +218,7 @@ cpu_init_crit: bl lowlevel_init /* go setup memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +#endif /* ************************************************************************* * diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S index 0031461..bb1f003 100644 --- a/cpu/arm_intcm/start.S +++ b/cpu/arm_intcm/start.S @@ -131,7 +131,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifdef CONFIG_INIT_CRITICAL +#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif @@ -188,11 +188,13 @@ _start_armboot: ************************************************************************* */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* arm_int_generic assumes the ARM boot monitor, or user software, * has initialized the platform */ mov pc, lr /* back to my caller */ +#endif /* ************************************************************************* * -- cgit v1.1 From 2c75c78d94574ee996db2aa9b511258519471dd6 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:22 +0200 Subject: ixp/interrupts: Move conditional compilation to Makefile Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/ixp/Makefile | 3 ++- cpu/ixp/interrupts.c | 8 -------- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'cpu') diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile index 7e98d87..a673cb1 100644 --- a/cpu/ixp/Makefile +++ b/cpu/ixp/Makefile @@ -27,9 +27,10 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS-y += cpu.o -COBJS-y += interrupts.o ifndef CONFIG_USE_IRQ COBJS-y += timer.o +else +COBJS-y += interrupts.o endif SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index 621f31b..ee0129e 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -31,8 +31,6 @@ #include #include - -#ifdef CONFIG_USE_IRQ #include /* @@ -85,20 +83,15 @@ void reset_timer (void) timestamp = 0; } -#endif /* #ifdef CONFIG_USE_IRQ */ - -#ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { int irq = next_irq(); IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); } -#endif int interrupt_init (void) { -#ifdef CONFIG_USE_IRQ int i; /* install default interrupt handlers */ @@ -119,7 +112,6 @@ int interrupt_init (void) /* enable timer irq */ *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); -#endif return (0); } -- cgit v1.1 From ac7260a4190315eba4a6e526c764f6cad0bbf8c5 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:22 +0200 Subject: at91rm9200: move reset code to reset.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/at91rm9200/Makefile | 14 ++++++-- cpu/arm920t/at91rm9200/interrupts.c | 37 ------------------- cpu/arm920t/at91rm9200/reset.c | 71 +++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 40 deletions(-) create mode 100644 cpu/arm920t/at91rm9200/reset.c (limited to 'cpu') diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index 67f17fa..161ca94 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -25,9 +25,17 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o usb.o spi.o -SOBJS = lowlevel_init.o +SOBJS += lowlevel_init.o + +COBJS += bcm5221.o +COBJS += dm9161.o +COBJS += ether.o +COBJS += i2c.o +COBJS += interrupts.o +COBJS += lxt972.o +COBJS += reset.o +COBJS += spi.o +COBJS += usb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c index cff4916..4c38a9a 100644 --- a/cpu/arm920t/at91rm9200/interrupts.c +++ b/cpu/arm920t/at91rm9200/interrupts.c @@ -45,8 +45,6 @@ AT91PS_TC tmr; static ulong timestamp; static ulong lastinc; -void board_reset(void) __attribute__((__weak__)); - int interrupt_init (void) { tmr = AT91C_BASE_TC0; @@ -160,38 +158,3 @@ ulong get_tbclk (void) tbclk = CONFIG_SYS_HZ; return tbclk; } - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - * or toggle a GPIO pin on the AT91RM9200DK board - */ -void reset_cpu (ulong ignored) -{ - -#if defined(CONFIG_AT91RM9200_USART) - /*shutdown the console to avoid strange chars during reset */ - serial_exit(); -#endif - - if (board_reset) - board_reset(); - - /* this is the way Linux does it */ - - /* FIXME: - * These defines should be moved into - * include/asm-arm/arch-at91rm9200/AT91RM9200.h - * as soon as the whitespace fix gets applied. - */ - #define AT91C_ST_RSTEN (0x1 << 16) - #define AT91C_ST_EXTEN (0x1 << 17) - #define AT91C_ST_WDRST (0x1 << 0) - #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */ - #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */ - - ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; - ST_CR = AT91C_ST_WDRST; - - while (1); - /* Never reached */ -} diff --git a/cpu/arm920t/at91rm9200/reset.c b/cpu/arm920t/at91rm9200/reset.c new file mode 100644 index 0000000..945ea2c --- /dev/null +++ b/cpu/arm920t/at91rm9200/reset.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void board_reset(void) __attribute__((__weak__)); + +/* + * Reset the cpu by setting up the watchdog timer and let him time out + * or toggle a GPIO pin on the AT91RM9200DK board + */ +void reset_cpu (ulong ignored) +{ + +#if defined(CONFIG_AT91RM9200_USART) + /*shutdown the console to avoid strange chars during reset */ + serial_exit(); +#endif + + if (board_reset) + board_reset(); + + /* this is the way Linux does it */ + + /* FIXME: + * These defines should be moved into + * include/asm-arm/arch-at91rm9200/AT91RM9200.h + * as soon as the whitespace fix gets applied. + */ + #define AT91C_ST_RSTEN (0x1 << 16) + #define AT91C_ST_EXTEN (0x1 << 17) + #define AT91C_ST_WDRST (0x1 << 0) + #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */ + #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */ + + ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; + ST_CR = AT91C_ST_WDRST; + + while (1); + /* Never reached */ +} -- cgit v1.1 From b1966982718347f67317b3fb356439743ca68a37 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:22 +0200 Subject: OMAP3: Remove dublicated interrupt code Remove duplicated interrupt code. Original, identical code can be found in lib_arm/interrupts.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Dirk Behme --- cpu/arm_cortexa8/omap3/interrupts.c | 128 ------------------------------------ 1 file changed, 128 deletions(-) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c index 742fe9c..3fe13fb 100644 --- a/cpu/arm_cortexa8/omap3/interrupts.c +++ b/cpu/arm_cortexa8/omap3/interrupts.c @@ -34,134 +34,6 @@ #include #include -#include - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts(void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp) - ::"memory"); -} - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts(void) -{ - unsigned long old, temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1":"=r"(old), "=r"(temp) - ::"memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts(void) -{ - return; -} -int disable_interrupts(void) -{ - return 0; -} -#endif - -void bad_mode(void) -{ - panic("Resetting CPU ...\n"); - reset_cpu(0); -} - -void show_regs(struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes(regs); - - printf("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer(regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf(" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled(regs) ? "on" : "off", - fast_interrupts_enabled(regs) ? "on" : "off", - processor_modes[processor_mode(regs)], - thumb_mode(regs) ? " (T)" : ""); -} - -void do_undefined_instruction(struct pt_regs *pt_regs) -{ - printf("undefined instruction\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_software_interrupt(struct pt_regs *pt_regs) -{ - printf("software interrupt\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_prefetch_abort(struct pt_regs *pt_regs) -{ - printf("prefetch abort\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_data_abort(struct pt_regs *pt_regs) -{ - printf("data abort\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_not_used(struct pt_regs *pt_regs) -{ - printf("not used\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_fiq(struct pt_regs *pt_regs) -{ - printf("fast interrupt request\n"); - show_regs(pt_regs); - bad_mode(); -} - -void do_irq(struct pt_regs *pt_regs) -{ - printf("interrupt request\n"); - show_regs(pt_regs); - bad_mode(); -} - static ulong timestamp; static ulong lastinc; -- cgit v1.1 From 5b4bebe1d20c4f2b70d48b06aed1016785efcc25 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:45:22 +0200 Subject: OMAP3: Reorganize Makefile style Reformat COBJS handling. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Dirk Behme --- cpu/arm_cortexa8/omap3/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..d1e658d 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o + +COBJS += board.o +COBJS += clock.o +COBJS += mem.o +COBJS += syslib.o +COBJS += sys_info.o +COBJS += interrupts.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -- cgit v1.1 From b54384e3ba6b5535751f317fcd3940a53eed0d3a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:47:02 +0200 Subject: arm: timer and interrupt init rework actually the timer init use the interrupt_init as init callback which make the interrupt and timer implementation difficult to follow so now rename it as int timer_init(void) and use interrupt_init for interrupt btw also remane the corresponding file to the functionnality implemented as ixp arch implement two timer - one based on interrupt - so all the timer related code is moved to timer.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm1136/mx31/Makefile | 3 +- cpu/arm1136/mx31/interrupts.c | 171 --------------------------- cpu/arm1136/mx31/timer.c | 170 +++++++++++++++++++++++++++ cpu/arm1136/omap24xx/Makefile | 3 +- cpu/arm1136/omap24xx/interrupts.c | 159 ------------------------- cpu/arm1136/omap24xx/timer.c | 158 +++++++++++++++++++++++++ cpu/arm1176/s3c64xx/Makefile | 2 +- cpu/arm1176/s3c64xx/interrupts.c | 177 ---------------------------- cpu/arm1176/s3c64xx/timer.c | 177 ++++++++++++++++++++++++++++ cpu/arm720t/interrupts.c | 46 ++++---- cpu/arm920t/at91rm9200/Makefile | 2 +- cpu/arm920t/at91rm9200/interrupts.c | 160 ------------------------- cpu/arm920t/at91rm9200/timer.c | 160 +++++++++++++++++++++++++ cpu/arm920t/imx/Makefile | 4 +- cpu/arm920t/imx/interrupts.c | 139 ---------------------- cpu/arm920t/imx/timer.c | 139 ++++++++++++++++++++++ cpu/arm920t/ks8695/Makefile | 3 +- cpu/arm920t/ks8695/interrupts.c | 112 ------------------ cpu/arm920t/ks8695/timer.c | 108 +++++++++++++++++ cpu/arm920t/s3c24x0/Makefile | 5 +- cpu/arm920t/s3c24x0/interrupts.c | 228 ------------------------------------ cpu/arm920t/s3c24x0/timer.c | 228 ++++++++++++++++++++++++++++++++++++ cpu/arm925t/Makefile | 5 +- cpu/arm925t/interrupts.c | 137 ---------------------- cpu/arm925t/timer.c | 137 ++++++++++++++++++++++ cpu/arm926ejs/Makefile | 2 +- cpu/arm926ejs/interrupts.c | 57 --------- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/interrupts.c | 138 ---------------------- cpu/arm_cortexa8/omap3/timer.c | 138 ++++++++++++++++++++++ cpu/ixp/Makefile | 6 +- cpu/ixp/interrupts.c | 55 ++------- cpu/ixp/timer.c | 54 +++++++++ cpu/lh7a40x/Makefile | 2 +- cpu/lh7a40x/interrupts.c | 194 ------------------------------ cpu/lh7a40x/timer.c | 194 ++++++++++++++++++++++++++++++ cpu/pxa/Makefile | 8 +- cpu/pxa/interrupts.c | 127 -------------------- cpu/pxa/timer.c | 128 ++++++++++++++++++++ cpu/s3c44b0/Makefile | 5 +- cpu/s3c44b0/interrupts.c | 136 --------------------- cpu/s3c44b0/timer.c | 136 +++++++++++++++++++++ cpu/sa1100/Makefile | 4 +- cpu/sa1100/interrupts.c | 111 ------------------ cpu/sa1100/timer.c | 110 +++++++++++++++++ 45 files changed, 2111 insertions(+), 2129 deletions(-) delete mode 100644 cpu/arm1136/mx31/interrupts.c create mode 100644 cpu/arm1136/mx31/timer.c delete mode 100644 cpu/arm1136/omap24xx/interrupts.c create mode 100644 cpu/arm1136/omap24xx/timer.c delete mode 100644 cpu/arm1176/s3c64xx/interrupts.c create mode 100644 cpu/arm1176/s3c64xx/timer.c delete mode 100644 cpu/arm920t/at91rm9200/interrupts.c create mode 100644 cpu/arm920t/at91rm9200/timer.c delete mode 100644 cpu/arm920t/imx/interrupts.c create mode 100644 cpu/arm920t/imx/timer.c delete mode 100644 cpu/arm920t/ks8695/interrupts.c create mode 100644 cpu/arm920t/ks8695/timer.c delete mode 100644 cpu/arm920t/s3c24x0/interrupts.c create mode 100644 cpu/arm920t/s3c24x0/timer.c delete mode 100644 cpu/arm925t/interrupts.c create mode 100644 cpu/arm925t/timer.c delete mode 100644 cpu/arm926ejs/interrupts.c delete mode 100644 cpu/arm_cortexa8/omap3/interrupts.c create mode 100644 cpu/arm_cortexa8/omap3/timer.c delete mode 100644 cpu/lh7a40x/interrupts.c create mode 100644 cpu/lh7a40x/timer.c delete mode 100644 cpu/pxa/interrupts.c create mode 100644 cpu/pxa/timer.c delete mode 100644 cpu/s3c44b0/interrupts.c create mode 100644 cpu/s3c44b0/timer.c delete mode 100644 cpu/sa1100/interrupts.c create mode 100644 cpu/sa1100/timer.c (limited to 'cpu') diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index 0e06f0a..1e49e8d 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o generic.o +COBJS += generic.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c deleted file mode 100644 index ab7202f..0000000 --- a/cpu/arm1136/mx31/interrupts.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ - -/* General purpose timers registers */ -#define GPTCR __REG(TIMER_BASE) /* Control register */ -#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ -#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ -#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ - -static ulong timestamp; -static ulong lastinc; - -/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ -#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX31_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_MX31_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_MX31_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - -/* nothing really to do with interrupts, just starts up a counter. */ -/* The 32768Hz 32-bit timer overruns in 131072 seconds */ -int interrupt_init (void) -{ - int i; - - /* setup GP Timer 1 */ - GPTCR = GPTCR_SWR; - for (i = 0; i < 100; i++) - GPTCR = 0; /* We have no udelay by now */ - GPTPR = 0; /* 32Khz */ - /* Freerun Mode, PERCLK1 input */ - GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; - - return 0; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = GPTCNT; /* capture current incrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -unsigned long long get_ticks (void) -{ - ulong now = GPTCNT; /* current tick value */ - - if (now >= lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += (now - lastinc); - else /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - lastinc = now; - return timestamp; -} - -ulong get_timer_masked (void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = time_to_tick(t); -} - -/* delay x useconds AND perserve advance timstamp value */ -void udelay (unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -void reset_cpu (ulong addr) -{ - __REG16(WDOG_BASE) = 4; -} diff --git a/cpu/arm1136/mx31/timer.c b/cpu/arm1136/mx31/timer.c new file mode 100644 index 0000000..29b484e --- /dev/null +++ b/cpu/arm1136/mx31/timer.c @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ + +/* General purpose timers registers */ +#define GPTCR __REG(TIMER_BASE) /* Control register */ +#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_TEN 1 /* Timer enable */ + +static ulong timestamp; +static ulong lastinc; + +/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ +#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_MX31_CLK32); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + time *= CONFIG_MX31_CLK32; + do_div(time, CONFIG_SYS_HZ); + return time; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * CONFIG_MX31_CLK32 + 999999; + do_div(us, 1000000); + return us; +} +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + do_div(tick, TICK_PER_TIME); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + return time * TICK_PER_TIME; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us += US_PER_TICK - 1; + do_div(us, US_PER_TICK); + return us; +} +#endif + +/* The 32768Hz 32-bit timer overruns in 131072 seconds */ +int timer_init (void) +{ + int i; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ + GPTPR = 0; /* 32Khz */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; + + return 0; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = GPTCNT; /* capture current incrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long long get_ticks (void) +{ + ulong now = GPTCNT; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += (now - lastinc); + else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; +} + +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = time_to_tick(t); +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + +void reset_cpu (ulong addr) +{ + __REG16(WDOG_BASE) = 4; +} diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile index f9afed7..2a79d9b 100644 --- a/cpu/arm1136/omap24xx/Makefile +++ b/cpu/arm1136/omap24xx/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o SOBJS = start.o +COBJS = timer.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c deleted file mode 100644 index a0c535d..0000000 --- a/cpu/arm1136/omap24xx/interrupts.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define TIMER_LOAD_VAL 0 - -/* macro to read the 32 bit timer */ -#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))) - -static ulong timestamp; -static ulong lastinc; - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - int32_t val; - - /* Start the counter ticking up */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ - - reset_timer_masked(); /* init the timestamp and lastinc value */ - - return(0); -} -/* - * timer without interrupts - */ -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND perserve advance timstamp value */ -void udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (now >= lastinc) /* normal mode (non roll) */ - timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ - else /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - lastinc = now; - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/cpu/arm1136/omap24xx/timer.c b/cpu/arm1136/omap24xx/timer.c new file mode 100644 index 0000000..8dd8d7b --- /dev/null +++ b/cpu/arm1136/omap24xx/timer.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define TIMER_LOAD_VAL 0 + +/* macro to read the 32 bit timer */ +#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))) + +static ulong timestamp; +static ulong lastinc; + +int timer_init (void) +{ + int32_t val; + + /* Start the counter ticking up */ + *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ + val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ + + reset_timer_masked(); /* init the timestamp and lastinc value */ + + return(0); +} +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; /* capture current incrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ + timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ + else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile index fa4ee3f..4656d9a 100644 --- a/cpu/arm1176/s3c64xx/Makefile +++ b/cpu/arm1176/s3c64xx/Makefile @@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y = interrupts.o COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o +COBJS-y += timer.o OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/interrupts.c deleted file mode 100644 index 7bb9848..0000000 --- a/cpu/arm1176/s3c64xx/interrupts.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -static ulong timer_load_val; - -#define PRESCALER 167 - -static s3c64xx_timers *s3c64xx_get_base_timers(void) -{ - return (s3c64xx_timers *)ELFIN_TIMER_BASE; -} - -/* macro to read the 16 bit timer */ -static inline ulong read_timer(void) -{ - s3c64xx_timers *const timers = s3c64xx_get_base_timers(); - - return timers->TCNTO4; -} - -/* Internal tick units */ -/* Last decremneter snapshot */ -static unsigned long lastdec; -/* Monotonic incrementing timer */ -static unsigned long long timestamp; - -int interrupt_init(void) -{ - s3c64xx_timers *const timers = s3c64xx_get_base_timers(); - - /* use PWM Timer 4 because it has no output */ - /* - * We use the following scheme for the timer: - * Prescaler is hard fixed at 167, divider at 1/4. - * This gives at PCLK frequency 66MHz approx. 10us ticks - * The timer is set to wrap after 100s, at 66MHz this obviously - * happens after 10,000,000 ticks. A long variable can thus - * keep values up to 40,000s, i.e., 11 hours. This should be - * enough for most uses:-) Possible optimizations: select a - * binary-friendly frequency, e.g., 1ms / 128. Also calculate - * the prescaler automatically for other PCLK frequencies. - */ - timers->TCFG0 = PRESCALER << 8; - if (timer_load_val == 0) { - timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */ - timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000; - } - - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | - TCON_4_UPDATE; - - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON; - timestamp = 0; - - return 0; -} - -/* - * timer without interrupts - */ - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - /* We overrun in 100s */ - return (ulong)(timer_load_val / 100); -} - -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = read_timer(); - timestamp = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer_masked(void) -{ - unsigned long long res = get_ticks(); - do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ))); - return res; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ)); -} - -void udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = (usec + 9) / 10; - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp)/* loop till event */ - /*NOP*/; -} diff --git a/cpu/arm1176/s3c64xx/timer.c b/cpu/arm1176/s3c64xx/timer.c new file mode 100644 index 0000000..22a5b77 --- /dev/null +++ b/cpu/arm1176/s3c64xx/timer.c @@ -0,0 +1,177 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static ulong timer_load_val; + +#define PRESCALER 167 + +static s3c64xx_timers *s3c64xx_get_base_timers(void) +{ + return (s3c64xx_timers *)ELFIN_TIMER_BASE; +} + +/* macro to read the 16 bit timer */ +static inline ulong read_timer(void) +{ + s3c64xx_timers *const timers = s3c64xx_get_base_timers(); + + return timers->TCNTO4; +} + +/* Internal tick units */ +/* Last decremneter snapshot */ +static unsigned long lastdec; +/* Monotonic incrementing timer */ +static unsigned long long timestamp; + +int timer_init(void) +{ + s3c64xx_timers *const timers = s3c64xx_get_base_timers(); + + /* use PWM Timer 4 because it has no output */ + /* + * We use the following scheme for the timer: + * Prescaler is hard fixed at 167, divider at 1/4. + * This gives at PCLK frequency 66MHz approx. 10us ticks + * The timer is set to wrap after 100s, at 66MHz this obviously + * happens after 10,000,000 ticks. A long variable can thus + * keep values up to 40,000s, i.e., 11 hours. This should be + * enough for most uses:-) Possible optimizations: select a + * binary-friendly frequency, e.g., 1ms / 128. Also calculate + * the prescaler automatically for other PCLK frequencies. + */ + timers->TCFG0 = PRESCALER << 8; + if (timer_load_val == 0) { + timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */ + timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000; + } + + /* load value for 10 ms timeout */ + lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ + timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | + TCON_4_UPDATE; + + /* auto load, start Timer 4 */ + timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON; + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + ulong now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + timer_load_val - now; + } + lastdec = now; + + return timestamp; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + /* We overrun in 100s */ + return (ulong)(timer_load_val / 100); +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = read_timer(); + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer_masked(void) +{ + unsigned long long res = get_ticks(); + do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ))); + return res; +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ)); +} + +void udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = (usec + 9) / 10; + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp)/* loop till event */ + /*NOP*/; +} diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..ff21314 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -110,9 +110,34 @@ static void timer_isr( void *data) { static ulong timestamp; static ulong lastdec; +#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B) int interrupt_init (void) { + int i; + + /* install default interrupt handlers */ + for ( i = 0; i < N_IRQS; i++) { + IRQ_HANDLER[i].m_data = (void *)i; + IRQ_HANDLER[i].m_func = default_isr; + } + + /* configure interrupts for IRQ mode */ + PUT_REG( REG_INTMODE, 0x0); + /* clear any pending interrupts */ + PUT_REG( REG_INTPEND, 0x1FFFFF); + + lastdec = 0; + + /* install interrupt handler for timer */ + IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; + IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; + + return 0; +} +#endif +int timer_init (void) +{ #if defined(CONFIG_NETARM) /* disable all interrupts */ IRQEN = 0; @@ -137,25 +162,6 @@ int interrupt_init (void) /* set timer 1 counter */ lastdec = IO_TC1D = TIMER_LOAD_VAL; #elif defined(CONFIG_S3C4510B) - int i; - - /* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); - /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); - - lastdec = 0; - - /* install interrupt handler for timer */ - IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; - IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; - /* configure free running timer 0 */ PUT_REG( REG_TMOD, 0x0); /* Stop timer 0 */ @@ -187,7 +193,7 @@ int interrupt_init (void) PUT32(T0TCR, 1); /* enable timer0 */ #else -#error No interrupt_init() defined for this CPU type +#error No timer_init() defined for this CPU type #endif timestamp = 0; diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index 161ca94..73aeeac 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -31,10 +31,10 @@ COBJS += bcm5221.o COBJS += dm9161.o COBJS += ether.o COBJS += i2c.o -COBJS += interrupts.o COBJS += lxt972.o COBJS += reset.o COBJS += spi.o +COBJS += timer.o COBJS += usb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c deleted file mode 100644 index 4c38a9a..0000000 --- a/cpu/arm920t/at91rm9200/interrupts.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -/*#include */ -#include -/*#include */ - -/* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) - -/* macro to read the 16 bit timer */ -#define READ_TIMER (tmr->TC_CV & 0x0000ffff) -AT91PS_TC tmr; - -static ulong timestamp; -static ulong lastinc; - -int interrupt_init (void) -{ - tmr = AT91C_BASE_TC0; - - /* enables TC1.0 clock */ - *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ - - *AT91C_TCB0_BCR = 0; - *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; - tmr->TC_CCR = AT91C_TC_CLKDIS; -#define AT91C_TC_CMR_CPCTRG (1 << 14) - /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ - tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; - - tmr->TC_IDR = ~0ul; - tmr->TC_RC = TIMER_LOAD_VAL; - lastinc = 0; - tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_raw (void) -{ - ulong now = READ_TIMER; - - if (now >= lastinc) { - /* normal mode */ - timestamp += now - lastinc; - } else { - /* we have an overflow ... */ - timestamp += now + TIMER_LOAD_VAL - lastinc; - } - lastinc = now; - - return timestamp; -} - -ulong get_timer_masked (void) -{ - return get_timer_raw()/TIMER_LOAD_VAL; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= 1000; - - endtime = get_timer_raw () + tmo; - - do { - ulong now = get_timer_raw (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/cpu/arm920t/at91rm9200/timer.c b/cpu/arm920t/at91rm9200/timer.c new file mode 100644 index 0000000..235d107 --- /dev/null +++ b/cpu/arm920t/at91rm9200/timer.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +/*#include */ +#include +/*#include */ + +/* the number of clocks per CONFIG_SYS_HZ */ +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) + +/* macro to read the 16 bit timer */ +#define READ_TIMER (tmr->TC_CV & 0x0000ffff) +AT91PS_TC tmr; + +static ulong timestamp; +static ulong lastinc; + +int timer_init (void) +{ + tmr = AT91C_BASE_TC0; + + /* enables TC1.0 clock */ + *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ + + *AT91C_TCB0_BCR = 0; + *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; + tmr->TC_CCR = AT91C_TC_CLKDIS; +#define AT91C_TC_CMR_CPCTRG (1 << 14) + /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ + tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; + + tmr->TC_IDR = ~0ul; + tmr->TC_RC = TIMER_LOAD_VAL; + lastinc = 0; + tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_raw (void) +{ + ulong now = READ_TIMER; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* we have an overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + + return timestamp; +} + +ulong get_timer_masked (void) +{ + return get_timer_raw()/TIMER_LOAD_VAL; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw () + tmo; + + do { + ulong now = get_timer_raw (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile index d3352de..28945e2 100644 --- a/cpu/arm920t/imx/Makefile +++ b/cpu/arm920t/imx/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = generic.o interrupts.o speed.o +COBJS += generic.o +COBJS += speed.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c deleted file mode 100644 index 1beaf9d..0000000 --- a/cpu/arm920t/imx/interrupts.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined (CONFIG_IMX) - -#include -#include - -int interrupt_init (void) -{ - int i; - /* setup GP Timer 1 */ - TCTL1 = TCTL_SWR; - for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ - TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ - TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ - - reset_timer_masked(); - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void reset_timer_masked (void) -{ - TCTL1 &= ~TCTL_TEN; - TCTL1 |= TCTL_TEN; /* Enable timer */ -} - -ulong get_timer_masked (void) -{ - return TCN1; -} - -void udelay_masked (unsigned long usec) -{ - ulong endtime = get_timer_masked() + usec; - signed long diff; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -void udelay (unsigned long usec) -{ - udelay_masked(usec); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - - return tbclk; -} - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu (ulong ignored) -{ - /* Disable watchdog and set Time-Out field to 0 */ - WCR = 0x00000000; - - /* Write Service Sequence */ - WSR = 0x00005555; - WSR = 0x0000AAAA; - - /* Enable watchdog */ - WCR = 0x00000001; - - while (1); - /*NOTREACHED*/ -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/imx/timer.c b/cpu/arm920t/imx/timer.c new file mode 100644 index 0000000..280c682 --- /dev/null +++ b/cpu/arm920t/imx/timer.c @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined (CONFIG_IMX) + +#include +#include + +int timer_init (void) +{ + int i; + /* setup GP Timer 1 */ + TCTL1 = TCTL_SWR; + for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ + TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ + TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ + + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void reset_timer_masked (void) +{ + TCTL1 &= ~TCTL_TEN; + TCTL1 |= TCTL_TEN; /* Enable timer */ +} + +ulong get_timer_masked (void) +{ + return TCN1; +} + +void udelay_masked (unsigned long usec) +{ + ulong endtime = get_timer_masked() + usec; + signed long diff; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +void udelay (unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + + return tbclk; +} + +/* + * Reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + /* Disable watchdog and set Time-Out field to 0 */ + WCR = 0x00000000; + + /* Write Service Sequence */ + WSR = 0x00005555; + WSR = 0x0000AAAA; + + /* Enable watchdog */ + WCR = 0x00000001; + + while (1); + /*NOTREACHED*/ +} + +#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile index f6b0063..f53fdc2 100644 --- a/cpu/arm920t/ks8695/Makefile +++ b/cpu/arm920t/ks8695/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o SOBJS = lowlevel_init.o +COBJS = timer.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/interrupts.c deleted file mode 100644 index 883d689..0000000 --- a/cpu/arm920t/ks8695/interrupts.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -int timer_inited; -ulong timer_ticks; - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -void reset_timer_masked(void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - timer_inited++; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void set_timer(ulong t) -{ - timer_ticks = t; -} - -void udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - if (!timer_inited) - reset_timer(); - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/cpu/arm920t/ks8695/timer.c b/cpu/arm920t/ks8695/timer.c new file mode 100644 index 0000000..22987bc --- /dev/null +++ b/cpu/arm920t/ks8695/timer.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2004-2005, Greg Ungerer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Handy KS8695 register access functions. + */ +#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) +#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) + +ulong timer_ticks; + +int timer_init (void) +{ + reset_timer(); + + return 0; +} + +/* + * Initial timer set constants. Nothing complicated, just set for a 1ms + * tick. + */ +#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) +#define TIMER_COUNT (TIMER_INTERVAL / 2) +#define TIMER_PULSE TIMER_COUNT + +void reset_timer_masked(void) +{ + /* Set the hadware timer for 1ms */ + ks8695_write(KS8695_TIMER1, TIMER_COUNT); + ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); + ks8695_write(KS8695_TIMER_CTRL, 0x2); + timer_ticks = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer_masked(void) +{ + /* Check for timer wrap */ + if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { + /* Clear interrupt condition */ + ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); + timer_ticks++; + } + return timer_ticks; +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() - base); +} + +void set_timer(ulong t) +{ + timer_ticks = t; +} + +void udelay(ulong usec) +{ + ulong start = get_timer_masked(); + ulong end; + + /* Only 1ms resolution :-( */ + end = usec / 1000; + while (get_timer(start) < end) + ; +} + +void reset_cpu (ulong ignored) +{ + ulong tc; + + /* Set timer0 to watchdog, and let it timeout */ + tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; + ks8695_write(KS8695_TIMER_CTRL, tc); + ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); + ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); + + /* Should only wait here till watchdog resets */ + for (;;) + ; +} diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 3afe19c..5d2be2c 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o speed.o usb.o usb_ohci.o +COBJS += speed.o +COBJS += timer.o +COBJS += usb.o +COBJS += usb_ohci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c deleted file mode 100644 index b8ce6ae..0000000 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - -#include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - -int timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - return (timers->TCNTO4 & 0xffff); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - /* use PWM Timer 4 because it has no output */ - /* prescaler for Timer 4 is 16 */ - timers->TCFG0 = 0x0f00; - if (timer_load_val == 0) - { - /* - * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 - * (default) and prescaler = 16. Should be 10390 - * @33.25MHz and 15625 @ 50 MHz - */ - timer_load_val = get_PCLK()/(2 * 16 * 100); - } - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - ulong start = get_timer(0); - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - while ((ulong)(get_timer_masked () - start) < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - } else { - tmo = usec * (timer_load_val * 100); - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - -#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SBC2410X) || \ - defined(CONFIG_SMDK2410) || \ - defined(CONFIG_VCMA9) - tbclk = CONFIG_SYS_HZ; -#else -# error "tbclk not configured" -#endif - - return tbclk; -} - -/* - * reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu (ulong ignored) -{ - volatile S3C24X0_WATCHDOG * watchdog; - -#ifdef CONFIG_TRAB - extern void disable_vfd (void); - - disable_vfd(); -#endif - - watchdog = S3C24X0_GetBase_WATCHDOG(); - - /* Disable watchdog */ - watchdog->WTCON = 0x0000; - - /* Initialize watchdog timer count register */ - watchdog->WTCNT = 0x0001; - - /* Enable watchdog timer; assert reset at timer timeout */ - watchdog->WTCON = 0x0021; - - while(1); /* loop forever and wait for reset to happen */ - - /*NOTREACHED*/ -} - -#ifdef CONFIG_USE_IRQ -void s3c2410_irq(void) -{ - S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); - u_int32_t intpnd = irq->INTPND; - -} -#endif /* USE_IRQ */ - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c new file mode 100644 index 0000000..f3c0ed6 --- /dev/null +++ b/cpu/arm920t/s3c24x0/timer.c @@ -0,0 +1,228 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + +#include +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +int timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + return (timers->TCNTO4 & 0xffff); +} + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + /* use PWM Timer 4 because it has no output */ + /* prescaler for Timer 4 is 16 */ + timers->TCFG0 = 0x0f00; + if (timer_load_val == 0) + { + /* + * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 + * (default) and prescaler = 16. Should be 10390 + * @33.25MHz and 15625 @ 50 MHz + */ + timer_load_val = get_PCLK()/(2 * 16 * 100); + } + /* load value for 10 ms timeout */ + lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; + /* auto load, start Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + while ((ulong)(get_timer_masked () - start) < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + timer_load_val - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + } else { + tmo = usec * (timer_load_val * 100); + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + +#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) + tbclk = timer_load_val * 100; +#elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SMDK2410) || \ + defined(CONFIG_VCMA9) + tbclk = CONFIG_SYS_HZ; +#else +# error "tbclk not configured" +#endif + + return tbclk; +} + +/* + * reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + volatile S3C24X0_WATCHDOG * watchdog; + +#ifdef CONFIG_TRAB + extern void disable_vfd (void); + + disable_vfd(); +#endif + + watchdog = S3C24X0_GetBase_WATCHDOG(); + + /* Disable watchdog */ + watchdog->WTCON = 0x0000; + + /* Initialize watchdog timer count register */ + watchdog->WTCNT = 0x0001; + + /* Enable watchdog timer; assert reset at timer timeout */ + watchdog->WTCON = 0x0021; + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#ifdef CONFIG_USE_IRQ +void s3c2410_irq(void) +{ + S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); + u_int32_t intpnd = irq->INTPND; + +} +#endif /* USE_IRQ */ + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile index 0d4912c..8d0e88f 100644 --- a/cpu/arm925t/Makefile +++ b/cpu/arm925t/Makefile @@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o omap925.o + +COBJS += cpu.o +COBJS += omap925.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c deleted file mode 100644 index 179992d..0000000 --- a/cpu/arm925t/interrupts.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2009 - * 2N Telekomunikace, - * - * (C) Copyright 2003 - * Texas Instruments, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) - -static uint32_t timestamp; -static uint32_t lastdec; - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - /* Start the decrementer ticking down from 0xffffffff */ - __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); - __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | - (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), - CONFIG_SYS_TIMERBASE + CNTL_TIMER); - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - return 0; -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND preserve advance timestamp value */ -void udelay (unsigned long usec) -{ - int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000; - uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); - - while (tmo > 0) { - now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); - if (last < now) /* count down timer underflow */ - tmo -= TIMER_LOAD_VAL - now + last; - else - tmo -= last - now; - last = now; - } -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - if (lastdec < now) /* count down timer underflow */ - timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) - - now + lastdec; - else - timestamp += lastdec - now; - lastdec = now; - - return timestamp; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return CONFIG_SYS_HZ; -} diff --git a/cpu/arm925t/timer.c b/cpu/arm925t/timer.c new file mode 100644 index 0000000..c16ef25 --- /dev/null +++ b/cpu/arm925t/timer.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2009 + * 2N Telekomunikace, + * + * (C) Copyright 2003 + * Texas Instruments, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) + +static uint32_t timestamp; +static uint32_t lastdec; + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init (void) +{ + /* Start the decrementer ticking down from 0xffffffff */ + __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); + __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | + (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), + CONFIG_SYS_TIMERBASE + CNTL_TIMER); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND preserve advance timestamp value */ +void udelay (unsigned long usec) +{ + int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000; + uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); + + while (tmo > 0) { + now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); + if (last < now) /* count down timer underflow */ + tmo -= TIMER_LOAD_VAL - now + last; + else + tmo -= last - now; + last = now; + } +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / + (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / + (TIMER_CLOCK / CONFIG_SYS_HZ); + if (lastdec < now) /* count down timer underflow */ + timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) - + now + lastdec; + else + timestamp += lastdec - now; + lastdec = now; + + return timestamp; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index d5ac7d3..7701b03 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o +COBJS = cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c deleted file mode 100644 index ce979f3..0000000 --- a/cpu/arm926ejs/interrupts.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_INTEGRATOR - - /* Timer functionality supplied by Integrator board (AP or CP) */ - -#else - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - extern void timer_init(void); - - timer_init(); - - return 0; -} - -#endif /* CONFIG_INTEGRATOR */ diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index d1e658d..edf5cb2 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -32,7 +32,7 @@ COBJS += clock.o COBJS += mem.o COBJS += syslib.o COBJS += sys_info.o -COBJS += interrupts.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c deleted file mode 100644 index 3fe13fb..0000000 --- a/cpu/arm_cortexa8/omap3/interrupts.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments - * - * Richard Woodruff - * Syed Moahmmed Khasim - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -static ulong timestamp; -static ulong lastinc; -static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; - -/* - * Nothing really to do with interrupts, just starts up a counter. - * We run the counter with 13MHz, divided by 8, resulting in timer - * frequency of 1.625MHz. With 32bit counter register, counter - * overflows in ~44min - */ - -/* 13MHz / 8 = 1.625MHz */ -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0xffffffff - -int interrupt_init(void) -{ - /* start the counter ticking up, reload value on overflow */ - writel(TIMER_LOAD_VAL, &timer_base->tldr); - /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - &timer_base->tclr); - - reset_timer_masked(); /* init the timestamp and lastinc value */ - - return 0; -} - -/* - * timer without interrupts - */ -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - timestamp = t; -} - -/* delay x useconds */ -void udelay(unsigned long usec) -{ - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&timer_base->tcrr); - - while (tmo > 0) { - now = readl(&timer_base->tcrr); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_LOAD_VAL - last + now; - else - tmo -= now - last; - last = now; - } -} - -void reset_timer_masked(void) -{ - /* reset time, capture current incrementer value time */ - lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - if (now >= lastinc) /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - timestamp += (now - lastinc); - else /* we have rollover of incrementer */ - timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) - - lastinc) + now; - lastinc = now; - return timestamp; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/cpu/arm_cortexa8/omap3/timer.c b/cpu/arm_cortexa8/omap3/timer.c new file mode 100644 index 0000000..05cfe76 --- /dev/null +++ b/cpu/arm_cortexa8/omap3/timer.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2008 + * Texas Instruments + * + * Richard Woodruff + * Syed Moahmmed Khasim + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static ulong timestamp; +static ulong lastinc; +static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; + +/* + * Nothing really to do with interrupts, just starts up a counter. + * We run the counter with 13MHz, divided by 8, resulting in timer + * frequency of 1.625MHz. With 32bit counter register, counter + * overflows in ~44min + */ + +/* 13MHz / 8 = 1.625MHz */ +#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init(void) +{ + /* start the counter ticking up, reload value on overflow */ + writel(TIMER_LOAD_VAL, &timer_base->tldr); + /* enable timer */ + writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + &timer_base->tclr); + + reset_timer_masked(); /* init the timestamp and lastinc value */ + + return 0; +} + +/* + * timer without interrupts + */ +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds */ +void udelay(unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&timer_base->tcrr); + + while (tmo > 0) { + now = readl(&timer_base->tcrr); + if (last > now) /* count up timer overflow */ + tmo -= TIMER_LOAD_VAL - last + now; + else + tmo -= now - last; + last = now; + } +} + +void reset_timer_masked(void) +{ + /* reset time, capture current incrementer value time */ + lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + if (now >= lastinc) /* normal mode (non roll) */ + /* move stamp fordward with absoulte diff ticks */ + timestamp += (now - lastinc); + else /* we have rollover of incrementer */ + timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) + - lastinc) + now; + lastinc = now; + return timestamp; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile index a673cb1..1403c4f 100644 --- a/cpu/ixp/Makefile +++ b/cpu/ixp/Makefile @@ -26,12 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o + COBJS-y += cpu.o -ifndef CONFIG_USE_IRQ +COBJS-$(CONFIG_USE_IRQ) += interrupts.o COBJS-y += timer.o -else -COBJS-y += interrupts.o -endif SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index ee0129e..a05e439 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -33,14 +33,6 @@ #include #include -/* - * When interrupts are enabled, use timer 2 for time/delay generation... - */ - -#define FREQ 66666666 -#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) -#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ - struct _irq_handler { void *m_data; void (*m_func)( void *data); @@ -48,8 +40,6 @@ struct _irq_handler { static struct _irq_handler IRQ_HANDLER[N_IRQS]; -static volatile ulong timestamp; - static void default_isr(void *data) { printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", @@ -61,33 +51,20 @@ static int next_irq(void) return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1); } -static void timer_isr(void *data) -{ - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - - /* - * Reset IRQ source - */ - *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; -} - -ulong get_timer (ulong base) +void do_irq (struct pt_regs *pt_regs) { - return timestamp - base; -} + int irq = next_irq(); -void reset_timer (void) -{ - timestamp = 0; + IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); } -void do_irq (struct pt_regs *pt_regs) +void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) { - int irq = next_irq(); + if (irq >= N_IRQS || !handle_irq) + return; - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); + IRQ_HANDLER[irq].m_data = data; + IRQ_HANDLER[irq].m_func = handle_irq; } int interrupt_init (void) @@ -95,23 +72,11 @@ int interrupt_init (void) int i; /* install default interrupt handlers */ - for (i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* install interrupt handler for timer */ - IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_data = (void *)×tamp; - IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_func = timer_isr; - - /* setup the Timer counter value */ - *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + for (i = 0; i < N_IRQS; i++) + irq_install_handler(i, default_isr, (void *)i); /* configure interrupts for IRQ mode */ *IXP425_ICLR = 0x00000000; - /* enable timer irq */ - *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); - return (0); } diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c index deb227a..6856149 100644 --- a/cpu/ixp/timer.c +++ b/cpu/ixp/timer.c @@ -32,6 +32,54 @@ #include #include +#ifdef CONFIG_TIMER_IRQ + +#define FREQ 66666666 +#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) +#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ + +/* + * When interrupts are enabled, use timer 2 for time/delay generation... + */ + +static volatile ulong timestamp; + +static void timer_isr(void *data) +{ + unsigned int *pTime = (unsigned int *)data; + + (*pTime)++; + + /* + * Reset IRQ source + */ + *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; +} + +ulong get_timer (ulong base) +{ + return timestamp - base; +} + +void reset_timer (void) +{ + timestamp = 0; +} + +int timer_init (void) +{ + /* install interrupt handler for timer */ + irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)×tamp); + + /* setup the Timer counter value */ + *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + + /* enable timer irq */ + *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); + + return 0; +} +#else ulong get_timer (ulong base) { return get_timer_masked () - base; @@ -79,3 +127,9 @@ ulong get_timer_masked (void) } return (reload_constant - current); } + +int timer_init(void) +{ + return 0; +} +#endif diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile index bac2a64..b9ae76e 100644 --- a/cpu/lh7a40x/Makefile +++ b/cpu/lh7a40x/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = cpu.o speed.o interrupts.o serial.o +COBJS = cpu.o speed.o serial.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c deleted file mode 100644 index d39e707..0000000 --- a/cpu/lh7a40x/interrupts.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -static ulong timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - return (timer->value & 0x0000ffff); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - /* a periodic timer using the 508kHz source */ - timer->control = (TIMER_PER | TIMER_CLK508K); - - if (timer_load_val == 0) { - /* - * 10ms period with 508.469kHz clock = 5084 - */ - timer_load_val = CONFIG_SYS_HZ/100; - } - - /* load value for 10 ms timeout */ - lastdec = timer->load = timer_load_val; - - /* auto load, start timer */ - timer->control = timer->control | TIMER_EN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return (get_timer_masked() - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } - else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += (lastdec - now); - } else { - /* we have an overflow ... */ - timestamp += ((lastdec + timer_load_val) - now); - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = timer_load_val * 100; - - return tbclk; -} diff --git a/cpu/lh7a40x/timer.c b/cpu/lh7a40x/timer.c new file mode 100644 index 0000000..f0baf14 --- /dev/null +++ b/cpu/lh7a40x/timer.c @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +static ulong timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; + lh7a40x_timer_t* timer = &timers->timer1; + + return (timer->value & 0x0000ffff); +} + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; + lh7a40x_timer_t* timer = &timers->timer1; + + /* a periodic timer using the 508kHz source */ + timer->control = (TIMER_PER | TIMER_CLK508K); + + if (timer_load_val == 0) { + /* + * 10ms period with 508.469kHz clock = 5084 + */ + timer_load_val = CONFIG_SYS_HZ/100; + } + + /* load value for 10 ms timeout */ + lastdec = timer->load = timer_load_val; + + /* auto load, start timer */ + timer->control = timer->control | TIMER_EN; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return (get_timer_masked() - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + } + else { + if (usec > 1) { + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += (lastdec - now); + } else { + /* we have an overflow ... */ + timestamp += ((lastdec + timer_load_val) - now); + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = timer_load_val * 100; + + return tbclk; +} diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile index 42903b2..5dc3a52 100644 --- a/cpu/pxa/Makefile +++ b/cpu/pxa/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o usb.o + +COBJS += cpu.o +COBJS += i2c.o +COBJS += pxafb.o +COBJS += serial.o +COBJS += timer.o +COBJS += usb.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c deleted file mode 100644 index 2bc5c50..0000000 --- a/cpu/pxa/interrupts.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_USE_IRQ -#error: interrupts not implemented yet -#endif - -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define TIMER_FREQ_HZ 3250000 -#elif defined(CONFIG_PXA250) -#define TIMER_FREQ_HZ 3686400 -#else -#error "Timer frequency unknown - please config PXA CPU type" -#endif - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); - return tick; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * TIMER_FREQ_HZ + 999999; - do_div(us, 1000000); - return us; -} - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - - -void reset_timer_masked (void) -{ - OSCR = 0; -} - -ulong get_timer_masked (void) -{ - return tick_to_time(get_ticks()); -} - -void udelay_masked (unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; - -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return OSCR; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = TIMER_FREQ_HZ; - return tbclk; -} diff --git a/cpu/pxa/timer.c b/cpu/pxa/timer.c new file mode 100644 index 0000000..e2df3a5 --- /dev/null +++ b/cpu/pxa/timer.c @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_USE_IRQ +#error: interrupts not implemented yet +#endif + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define TIMER_FREQ_HZ 3250000 +#elif defined(CONFIG_PXA250) +#define TIMER_FREQ_HZ 3686400 +#else +#error "Timer frequency unknown - please config PXA CPU type" +#endif + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ_HZ); + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * TIMER_FREQ_HZ + 999999; + do_div(us, 1000000); + return us; +} + +int timer_init (void) +{ + reset_timer(); + + return 0; +} + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + + +void reset_timer_masked (void) +{ + OSCR = 0; +} + +ulong get_timer_masked (void) +{ + return tick_to_time(get_ticks()); +} + +void udelay_masked (unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; + +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return OSCR; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = TIMER_FREQ_HZ; + return tbclk; +} diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile index ae909a6..6da2016 100644 --- a/cpu/s3c44b0/Makefile +++ b/cpu/s3c44b0/Makefile @@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = cache.o cpu.o interrupts.o + +COBJS += cache.o +COBJS += cpu.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c deleted file mode 100644 index eb23e6a..0000000 --- a/cpu/s3c44b0/interrupts.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff - -/* macro to read the 16 bit timer */ -#define READ_TIMER (TCNTO1 & 0xffff) - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ NOT supported -#endif - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - TCFG0 = 0x000000E9; - TCFG1 = 0x00000004; - TCON = 0x00000900; - TCNTB1 = TIMER_LOAD_VAL; - TCMPB1 = 0; - TCON = 0x00000B00; - TCON = 0x00000900; - - - lastdec = TCNTB1 = TIMER_LOAD_VAL; - timestamp = 0; - return 0; -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*8); - } - - endtime = get_timer(0) + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/cpu/s3c44b0/timer.c b/cpu/s3c44b0/timer.c new file mode 100644 index 0000000..34184ab --- /dev/null +++ b/cpu/s3c44b0/timer.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* we always count down the max. */ +#define TIMER_LOAD_VAL 0xffff + +/* macro to read the 16 bit timer */ +#define READ_TIMER (TCNTO1 & 0xffff) + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ NOT supported +#endif + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + TCFG0 = 0x000000E9; + TCFG1 = 0x00000004; + TCON = 0x00000900; + TCNTB1 = TIMER_LOAD_VAL; + TCMPB1 = 0; + TCON = 0x00000B00; + TCON = 0x00000900; + + + lastdec = TCNTB1 = TIMER_LOAD_VAL; + timestamp = 0; + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 8; + + tmo += get_timer (0); + + while (get_timer_masked () < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 8; + } else { + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*8); + } + + endtime = get_timer(0) + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile index fd696f7..28b6682 100644 --- a/cpu/sa1100/Makefile +++ b/cpu/sa1100/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o + +COBJS += cpu.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c deleted file mode 100644 index 2eff045..0000000 --- a/cpu/sa1100/interrupts.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - - -void reset_timer_masked (void) -{ - OSCR = 0; -} - -ulong get_timer_masked (void) -{ - return OSCR; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/cpu/sa1100/timer.c b/cpu/sa1100/timer.c new file mode 100644 index 0000000..3f77e81 --- /dev/null +++ b/cpu/sa1100/timer.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int timer_init (void) +{ + return 0; +} + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked (); +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + + +void reset_timer_masked (void) +{ + OSCR = 0; +} + +ulong get_timer_masked (void) +{ + return OSCR; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + } else { + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} -- cgit v1.1 From 7a4f511b59f08f51dde4ceacbd45f49b8bf2a5cc Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 15 May 2009 23:47:12 +0200 Subject: davinci: display correct clock info Move the clock-rate dumping code into the cpu/.../davinci area where it should have been, enabled by CONFIG_DISPLAY_CPUINFO, updating the format and showing the DSP clock (where relevant). Switch boards to use the cpuinfo() hook for this stuff. Remove a few now-obsolete PLL #defines. Signed-off-by: David Brownell --- cpu/arm926ejs/davinci/Makefile | 2 +- cpu/arm926ejs/davinci/cpu.c | 131 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 cpu/arm926ejs/davinci/cpu.c (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 480f19f..6eaa89c 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y += timer.o psc.o +COBJS-y += cpu.o timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c new file mode 100644 index 0000000..29aead6 --- /dev/null +++ b/cpu/arm926ejs/davinci/cpu.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2004 Texas Instruments. + * Copyright (C) 2009 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + + +/* offsets from PLL controller base */ +#define PLLC_PLLCTL 0x100 +#define PLLC_PLLM 0x110 +#define PLLC_PREDIV 0x114 +#define PLLC_PLLDIV1 0x118 +#define PLLC_PLLDIV2 0x11c +#define PLLC_PLLDIV3 0x120 +#define PLLC_POSTDIV 0x128 +#define PLLC_BPDIV 0x12c +#define PLLC_PLLDIV4 0x160 +#define PLLC_PLLDIV5 0x164 +#define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV8 0x170 +#define PLLC_PLLDIV9 0x174 + +#define BIT(x) (1 << (x)) + +/* SOC-specific pll info */ +#ifdef CONFIG_SOC_DM355 +#define ARM_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + +#ifdef CONFIG_SOC_DM644X +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DSP_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV2 +#endif + +#ifdef CONFIG_SOC_DM6447 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DSP_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + + +#ifdef CONFIG_DISPLAY_CPUINFO + +static unsigned pll_div(volatile void *pllbase, unsigned offset) +{ + u32 div; + + div = REG(pllbase + offset); + return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; +} + +static inline unsigned pll_prediv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + /* this register read seems to fail on pll0 */ + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return 8; + else + return pll_div(pllbase, PLLC_PREDIV); +#endif + return 1; +} + +static inline unsigned pll_postdiv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + return pll_div(pllbase, PLLC_POSTDIV); +#elif defined(CONFIG_SOC_DM6446) + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return pll_div(pllbase, PLLC_POSTDIV); +#endif + return 1; +} + +static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) +{ + volatile void *pllbase = (volatile void *) pll_addr; + unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; + + /* the PLL might be bypassed */ + if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { + base /= pll_prediv(pllbase); + base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); + base /= pll_postdiv(pllbase); + } + return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); +} + +int print_cpuinfo(void) +{ + /* REVISIT fetch and display CPU ID and revision information + * too ... that will matter as more revisions appear. + */ + printf("Cores: ARM %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); + +#ifdef DSP_PLLDIV + printf(", DSP %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); +#endif + + printf("\nDDR: %d MHz\n", + /* DDR PHY uses an x2 input clock */ + pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) + / 2); + return 0; +} + +#endif + -- cgit v1.1 From 2907798926ee932f453ac8538e7a6c05c18428a5 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 May 2009 23:47:13 +0200 Subject: arm920/926/926: remove non needed header Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/cpu.c | 1 - cpu/arm920t/imx/timer.c | 1 - cpu/arm920t/interrupts.c | 1 - cpu/arm920t/s3c24x0/timer.c | 1 - cpu/arm926ejs/cpu.c | 1 - cpu/arm926ejs/davinci/timer.c | 1 - cpu/arm926ejs/nomadik/timer.c | 1 - cpu/arm926ejs/omap/cpuinfo.c | 1 - cpu/arm926ejs/omap/timer.c | 1 - cpu/arm926ejs/versatile/timer.c | 1 - cpu/arm946es/cpu.c | 1 - cpu/lh7a40x/cpu.c | 1 - cpu/lh7a40x/timer.c | 1 - 13 files changed, 13 deletions(-) (limited to 'cpu') diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 0c080fe..b6ef6bb 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -31,7 +31,6 @@ #include #include -#include #include #ifdef CONFIG_USE_IRQ diff --git a/cpu/arm920t/imx/timer.c b/cpu/arm920t/imx/timer.c index 280c682..31ec588 100644 --- a/cpu/arm920t/imx/timer.c +++ b/cpu/arm920t/imx/timer.c @@ -32,7 +32,6 @@ #include #if defined (CONFIG_IMX) -#include #include int timer_init (void) diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index 1fbd1f0..ea24cdf 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -30,7 +30,6 @@ */ #include -#include #ifdef CONFIG_USE_IRQ #include diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index f3c0ed6..f0a09cd 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -32,7 +32,6 @@ #include #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) -#include #if defined(CONFIG_S3C2400) #include #elif defined(CONFIG_S3C2410) diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 518c5e0..1f70a36 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -31,7 +31,6 @@ #include #include -#include #include #ifdef CONFIG_USE_IRQ diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index 2604d57..80751ad 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -38,7 +38,6 @@ */ #include -#include typedef volatile struct { u_int32_t pid12; diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 960cf52..2870d24 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -37,7 +37,6 @@ #include #include -#include #define TIMER_LOAD_VAL 0xffffffff diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c index 35ba7db..0052dab 100644 --- a/cpu/arm926ejs/omap/cpuinfo.c +++ b/cpu/arm926ejs/omap/cpuinfo.c @@ -11,7 +11,6 @@ #include #include -#include #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c index 97f9771..392b158 100644 --- a/cpu/arm926ejs/omap/timer.c +++ b/cpu/arm926ejs/omap/timer.c @@ -36,7 +36,6 @@ */ #include -#include #define TIMER_LOAD_VAL 0xffffffff diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c index 6697672..50c1335 100755 --- a/cpu/arm926ejs/versatile/timer.c +++ b/cpu/arm926ejs/versatile/timer.c @@ -36,7 +36,6 @@ */ #include -#include #define TIMER_LOAD_VAL 0xffffffff diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index 04f0515..d3195f9 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -31,7 +31,6 @@ #include #include -#include #include #ifdef CONFIG_USE_IRQ diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 338df87..be92f70 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -31,7 +31,6 @@ #include #include -#include #include #ifdef CONFIG_USE_IRQ diff --git a/cpu/lh7a40x/timer.c b/cpu/lh7a40x/timer.c index f0baf14..f9b5be0 100644 --- a/cpu/lh7a40x/timer.c +++ b/cpu/lh7a40x/timer.c @@ -30,7 +30,6 @@ */ #include -#include #include static ulong timer_load_val = 0; -- cgit v1.1 From 68a531fd465f5c0b3d373e0010afed32e88d37c4 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Fri, 15 May 2009 23:47:52 +0200 Subject: OMAP Consolidate common u-boot.lds to cpu layer. The u-boot.lds file is common for all omap boards. Move a cleaned up version to the cpu layer and add makefile logic to use it. Signed-off-by: Tom Rix --- cpu/arm_cortexa8/omap3/config.mk | 2 ++ cpu/arm_cortexa8/omap3/u-boot.lds | 58 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 cpu/arm_cortexa8/omap3/u-boot.lds (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/config.mk b/cpu/arm_cortexa8/omap3/config.mk index 5fbec7a..9b028d8 100644 --- a/cpu/arm_cortexa8/omap3/config.mk +++ b/cpu/arm_cortexa8/omap3/config.mk @@ -34,3 +34,5 @@ PLATFORM_CPPFLAGS +=$(call cc-option) PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ $(call cc-option,-malignment-traps,)) + +LDSCRIPT := $(SRCTREE)/cpu/arm_cortexa8/omap3/u-boot.lds diff --git a/cpu/arm_cortexa8/omap3/u-boot.lds b/cpu/arm_cortexa8/omap3/u-boot.lds new file mode 100644 index 0000000..4f1711c --- /dev/null +++ b/cpu/arm_cortexa8/omap3/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} -- cgit v1.1 From 53925acf1b5c1a1e6230cda2697640cd05bd1104 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Fri, 15 May 2009 23:48:33 +0200 Subject: ARM DaVinci:Consolidate common u-boot.lds The u-boot.lds is common for all DaVinci boards. The patch removes multiple instances and moves the u-boot.lds to /cpu/arm926ejs/davinci folder. This addresses one of the comments i received while submitting patches for DM3xx Signed-off-by: Sandeep Paulraj --- cpu/arm926ejs/davinci/config.mk | 37 ++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/u-boot.lds | 52 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 cpu/arm926ejs/davinci/config.mk create mode 100644 cpu/arm926ejs/davinci/u-boot.lds (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk new file mode 100644 index 0000000..5221444 --- /dev/null +++ b/cpu/arm926ejs/davinci/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv5te +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) + +LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/davinci/u-boot.lds diff --git a/cpu/arm926ejs/davinci/u-boot.lds b/cpu/arm926ejs/davinci/u-boot.lds new file mode 100644 index 0000000..e50b8d4 --- /dev/null +++ b/cpu/arm926ejs/davinci/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} -- cgit v1.1 From 0c872ecd01d6782ae9d37b6eb721404a4a48f356 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Fri, 15 May 2009 23:48:36 +0200 Subject: OMAP3 Port kernel omap gpio interface. Port version 2.6.27 of the linux kernel's omap gpio interface to u-boot. The orignal source is in linux/arch/arm/plat-omap/gpio.c See doc/README.omap3 for instructions on use. Signed-off-by: Tom Rix --- cpu/arm_cortexa8/omap3/Makefile | 1 + cpu/arm_cortexa8/omap3/gpio.c | 185 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 cpu/arm_cortexa8/omap3/gpio.c (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index edf5cb2..50176ee 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o COBJS += board.o COBJS += clock.o +COBJS += gpio.o COBJS += mem.o COBJS += syslib.o COBJS += sys_info.o diff --git a/cpu/arm_cortexa8/omap3/gpio.c b/cpu/arm_cortexa8/omap3/gpio.c new file mode 100644 index 0000000..aeb6066 --- /dev/null +++ b/cpu/arm_cortexa8/omap3/gpio.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +static struct gpio_bank gpio_bank_34xx[6] = { + { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0]; + +static inline struct gpio_bank *get_gpio_bank(int gpio) +{ + return &gpio_bank[gpio >> 5]; +} + +static inline int get_gpio_index(int gpio) +{ + return gpio & 0x1f; +} + +static inline int gpio_valid(int gpio) +{ + if (gpio < 0) + return -1; + if (gpio < 192) + return 0; + return -1; +} + +static int check_gpio(int gpio) +{ + if (gpio_valid(gpio) < 0) { + printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); + return -1; + } + return 0; +} + +static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) +{ + void *reg = bank->base; + u32 l; + + switch (bank->method) { + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_OE; + break; + default: + return; + } + l = __raw_readl(reg); + if (is_input) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); +} + +void omap_set_gpio_direction(int gpio, int is_input) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + _set_gpio_direction(bank, get_gpio_index(gpio), is_input); +} + +static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) +{ + void *reg = bank->base; + u32 l = 0; + + switch (bank->method) { + case METHOD_GPIO_24XX: + if (enable) + reg += OMAP24XX_GPIO_SETDATAOUT; + else + reg += OMAP24XX_GPIO_CLEARDATAOUT; + l = 1 << gpio; + break; + default: + printf("omap3-gpio unknown bank method %s %d\n", + __FILE__, __LINE__); + return; + } + __raw_writel(l, reg); +} + +void omap_set_gpio_dataout(int gpio, int enable) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + _set_gpio_dataout(bank, get_gpio_index(gpio), enable); +} + +int omap_get_gpio_datain(int gpio) +{ + struct gpio_bank *bank; + void *reg; + + if (check_gpio(gpio) < 0) + return -EINVAL; + bank = get_gpio_bank(gpio); + reg = bank->base; + switch (bank->method) { + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_DATAIN; + break; + default: + return -EINVAL; + } + return (__raw_readl(reg) + & (1 << get_gpio_index(gpio))) != 0; +} + +static void _reset_gpio(struct gpio_bank *bank, int gpio) +{ + _set_gpio_direction(bank, get_gpio_index(gpio), 1); +} + +int omap_request_gpio(int gpio) +{ + if (check_gpio(gpio) < 0) + return -EINVAL; + + return 0; +} + +void omap_free_gpio(int gpio) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + + _reset_gpio(bank, gpio); +} -- cgit v1.1 From 1699da6297b8c22da16cf85b3c79192f1a6d70ca Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 13 May 2009 21:01:13 +0200 Subject: at91: regroup IP hw init in one file per soc Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm926ejs/at91/Makefile | 35 +----- cpu/arm926ejs/at91/at91cap9_devices.c | 176 +++++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91cap9_macb.c | 54 --------- cpu/arm926ejs/at91/at91cap9_serial.c | 76 ------------- cpu/arm926ejs/at91/at91cap9_spi.c | 100 ----------------- cpu/arm926ejs/at91/at91sam9260_devices.c | 184 +++++++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9260_macb.c | 63 ----------- cpu/arm926ejs/at91/at91sam9260_serial.c | 76 ------------- cpu/arm926ejs/at91/at91sam9260_spi.c | 99 ----------------- cpu/arm926ejs/at91/at91sam9261_devices.c | 148 +++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9261_serial.c | 76 ------------- cpu/arm926ejs/at91/at91sam9261_spi.c | 99 ----------------- cpu/arm926ejs/at91/at91sam9263_devices.c | 184 +++++++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9263_macb.c | 54 --------- cpu/arm926ejs/at91/at91sam9263_serial.c | 76 ------------- cpu/arm926ejs/at91/at91sam9263_spi.c | 99 ----------------- cpu/arm926ejs/at91/at91sam9263_usb.c | 35 ------ cpu/arm926ejs/at91/at91sam9rl_devices.c | 113 +++++++++++++++++++ cpu/arm926ejs/at91/at91sam9rl_serial.c | 76 ------------- cpu/arm926ejs/at91/at91sam9rl_spi.c | 64 ----------- 20 files changed, 811 insertions(+), 1076 deletions(-) create mode 100644 cpu/arm926ejs/at91/at91cap9_devices.c delete mode 100644 cpu/arm926ejs/at91/at91cap9_macb.c delete mode 100644 cpu/arm926ejs/at91/at91cap9_serial.c delete mode 100644 cpu/arm926ejs/at91/at91cap9_spi.c create mode 100644 cpu/arm926ejs/at91/at91sam9260_devices.c delete mode 100644 cpu/arm926ejs/at91/at91sam9260_macb.c delete mode 100644 cpu/arm926ejs/at91/at91sam9260_serial.c delete mode 100644 cpu/arm926ejs/at91/at91sam9260_spi.c create mode 100644 cpu/arm926ejs/at91/at91sam9261_devices.c delete mode 100644 cpu/arm926ejs/at91/at91sam9261_serial.c delete mode 100644 cpu/arm926ejs/at91/at91sam9261_spi.c create mode 100644 cpu/arm926ejs/at91/at91sam9263_devices.c delete mode 100644 cpu/arm926ejs/at91/at91sam9263_macb.c delete mode 100644 cpu/arm926ejs/at91/at91sam9263_serial.c delete mode 100644 cpu/arm926ejs/at91/at91sam9263_spi.c delete mode 100644 cpu/arm926ejs/at91/at91sam9263_usb.c create mode 100644 cpu/arm926ejs/at91/at91sam9rl_devices.c delete mode 100644 cpu/arm926ejs/at91/at91sam9rl_serial.c delete mode 100644 cpu/arm926ejs/at91/at91sam9rl_spi.c (limited to 'cpu') diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index e300d97..71acb0b 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -25,35 +25,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -ifdef CONFIG_AT91CAP9 -COBJS-$(CONFIG_MACB) += at91cap9_macb.o -COBJS-y += at91cap9_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91cap9_spi.o -endif -ifdef CONFIG_AT91SAM9260 -COBJS-$(CONFIG_MACB) += at91sam9260_macb.o -COBJS-y += at91sam9260_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9260_spi.o -endif -ifdef CONFIG_AT91SAM9G20 -COBJS-$(CONFIG_MACB) += at91sam9260_macb.o -COBJS-y += at91sam9260_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9260_spi.o -endif -ifdef CONFIG_AT91SAM9261 -COBJS-y += at91sam9261_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9261_spi.o -endif -ifdef CONFIG_AT91SAM9263 -COBJS-$(CONFIG_MACB) += at91sam9263_macb.o -COBJS-y += at91sam9263_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9263_spi.o -COBJS-$(CONFIG_USB_OHCI_NEW) += at91sam9263_usb.o -endif -ifdef CONFIG_AT91SAM9RL -COBJS-y += at91sam9rl_serial.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9rl_spi.o -endif +COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o +COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o +COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o +COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o +COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o +COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c new file mode 100644 index 0000000..c0024ac --- /dev/null +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_HAS_DATAFLASH +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_B_periph(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PD0, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PD1, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PD0, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD1, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB15, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PB16, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PB17, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PB18, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB15, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PB16, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PB17, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PB18, 1); + } + +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ +#endif +} +#endif diff --git a/cpu/arm926ejs/at91/at91cap9_macb.c b/cpu/arm926ejs/at91/at91cap9_macb.c deleted file mode 100644 index 5095d8d..0000000 --- a/cpu/arm926ejs/at91/at91cap9_macb.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_macb_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ - -#ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ -#endif -} diff --git a/cpu/arm926ejs/at91/at91cap9_serial.c b/cpu/arm926ejs/at91/at91cap9_serial.c deleted file mode 100644 index 5f41f7e..0000000 --- a/cpu/arm926ejs/at91/at91cap9_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_serial0_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); -} - -void at91_serial3_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} diff --git a/cpu/arm926ejs/at91/at91cap9_spi.c b/cpu/arm926ejs/at91/at91cap9_spi.c deleted file mode 100644 index cd8143b..0000000 --- a/cpu/arm926ejs/at91/at91cap9_spi.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); - - if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PD0, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD1, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PD0, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD1, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB15, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB16, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB17, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB18, 1); - } - -} diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c new file mode 100644 index 0000000..6dc0acc --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_HAS_DATAFLASH +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PC11, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PC16, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PC17, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PC11, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PC16, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PC17, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PC5, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PC4, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_gpio_output(AT91_PIN_PC3, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PC5, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PC4, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PC3, 1); + } +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ +#if defined(CONFIG_AT91SAM9260EK) + /* + * use PA10, PA11 for ETX2, ETX3. + * PA23 and PA24 are for TWI EEPROM + */ + at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ +#else + at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ +#endif + at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ +#endif +} +#endif diff --git a/cpu/arm926ejs/at91/at91sam9260_macb.c b/cpu/arm926ejs/at91/at91sam9260_macb.c deleted file mode 100644 index ea5e767..0000000 --- a/cpu/arm926ejs/at91/at91sam9260_macb.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_macb_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ - -#ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ -#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) - /* - * use PA10, PA11 for ETX2, ETX3. - * PA23 and PA24 are for TWI EEPROM - */ - at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ -#else - at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ -#endif - at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9260_serial.c b/cpu/arm926ejs/at91/at91sam9260_serial.c deleted file mode 100644 index 43f1971..0000000 --- a/cpu/arm926ejs/at91/at91sam9260_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_serial0_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); -} - -void at91_serial3_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9260_spi.c b/cpu/arm926ejs/at91/at91sam9260_spi.c deleted file mode 100644 index d6fd80e..0000000 --- a/cpu/arm926ejs/at91/at91sam9260_spi.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PC11, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PC16, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PC17, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PC11, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PC16, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PC17, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PC5, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PC4, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_gpio_output(AT91_PIN_PC3, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PC5, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PC4, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PC3, 1); - } -} diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c new file mode 100644 index 0000000..16d411f --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_HAS_DATAFLASH +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA4, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA6, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PA4, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PA6, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB28, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA24, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA25, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA26, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB28, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PA24, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PA25, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PA26, 1); + } +} +#endif diff --git a/cpu/arm926ejs/at91/at91sam9261_serial.c b/cpu/arm926ejs/at91/at91sam9261_serial.c deleted file mode 100644 index c262a92..0000000 --- a/cpu/arm926ejs/at91/at91sam9261_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_serial0_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); -} - -void at91_serial3_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9261_spi.c b/cpu/arm926ejs/at91/at91sam9261_spi.c deleted file mode 100644 index 9383dc6..0000000 --- a/cpu/arm926ejs/at91/at91sam9261_spi.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PA4, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA6, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA4, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PA6, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB28, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA24, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA25, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA26, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB28, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA24, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA25, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PA26, 1); - } -} diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c new file mode 100644 index 0000000..0f2613e --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_HAS_DATAFLASH +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_B_periph(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA4, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PB11, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PA5, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PA3, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PA4, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PB11, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB15, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PB16, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PB17, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PB18, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB15, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PB16, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PB17, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PB18, 1); + } +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ +#endif +} +#endif + +#ifdef CONFIG_USB_OHCI_NEW +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_gpio_output(AT91_PIN_PA21, 0); + at91_set_gpio_output(AT91_PIN_PA24, 0); +} +#endif diff --git a/cpu/arm926ejs/at91/at91sam9263_macb.c b/cpu/arm926ejs/at91/at91sam9263_macb.c deleted file mode 100644 index 4223d37..0000000 --- a/cpu/arm926ejs/at91/at91sam9263_macb.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_macb_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ - at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ - -#ifndef CONFIG_RMII - at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9263_serial.c b/cpu/arm926ejs/at91/at91sam9263_serial.c deleted file mode 100644 index 1076195..0000000 --- a/cpu/arm926ejs/at91/at91sam9263_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_serial0_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); -} - -void at91_serial3_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9263_spi.c b/cpu/arm926ejs/at91/at91sam9263_spi.c deleted file mode 100644 index e52dd61..0000000 --- a/cpu/arm926ejs/at91/at91sam9263_spi.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); - - if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA4, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PB11, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA4, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB11, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB15, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB16, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB17, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB18, 1); - } -} diff --git a/cpu/arm926ejs/at91/at91sam9263_usb.c b/cpu/arm926ejs/at91/at91sam9263_usb.c deleted file mode 100644 index ff5593b..0000000 --- a/cpu/arm926ejs/at91/at91sam9263_usb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -void at91_uhp_hw_init(void) -{ - /* Enable VBus on UHP ports */ - at91_set_gpio_output(AT91_PIN_PA21, 0); - at91_set_gpio_output(AT91_PIN_PA24, 0); -} diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c new file mode 100644 index 0000000..ebed193 --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_HAS_DATAFLASH +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA28, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PB7, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PD8, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PD9, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PA28, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PB7, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PD8, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD9, 1); + } +} +#endif diff --git a/cpu/arm926ejs/at91/at91sam9rl_serial.c b/cpu/arm926ejs/at91/at91sam9rl_serial.c deleted file mode 100644 index 99ce418..0000000 --- a/cpu/arm926ejs/at91/at91sam9rl_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_serial0_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); -} - -void at91_serial3_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} diff --git a/cpu/arm926ejs/at91/at91sam9rl_spi.c b/cpu/arm926ejs/at91/at91sam9rl_spi.c deleted file mode 100644 index 389d6d8..0000000 --- a/cpu/arm926ejs/at91/at91sam9rl_spi.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); - - if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA28, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PB7, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PD8, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD9, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA28, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB7, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PD8, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD9, 1); - } -} -- cgit v1.1 From 2ae0f35fd60c7345446835b95a4daff356e1f031 Mon Sep 17 00:00:00 2001 From: Thomas Lange Date: Sun, 3 May 2009 20:07:33 +0200 Subject: ARM DaVinci: Reset with watchdog enabled Once the Davinci watchdog has been enabled, the timeout value cannot be changed. If the timeout in use is long, it can take a long time for card to reset. By writing an invalid service key, we can trigger an immediate reset. Signed-off-by: Thomas Lange --- cpu/arm926ejs/davinci/reset.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S index a687d44..ba0a7c3 100644 --- a/cpu/arm926ejs/davinci/reset.S +++ b/cpu/arm926ejs/davinci/reset.S @@ -50,6 +50,10 @@ reset_cpu: str r1, [r0] ldr r1, WDTCR_VAL2 str r1, [r0] + /* Write an invalid value to the WDKEY field to trigger + * an immediate watchdog reset */ + mov r1, $0x4000 + str r1, [r0] nop nop nop -- cgit v1.1 From 1bbae2b816d4ed38db2ebf42166a973b1ffc0df7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 27 May 2009 10:34:32 +0200 Subject: ppc4xx: Remove PCI async bootup message if PCI is not used Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 9a6a8d7..06f44ad 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -597,7 +597,7 @@ int checkcpu (void) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif -#if defined(PCI_ASYNC) +#if defined(CONFIG_PCI) && defined(PCI_ASYNC) if (pci_async_enabled()) { printf (", PCI async ext clock used"); } else { -- cgit v1.1 From 9475c63c7855edd863c93a9bb0f4b8e240d9d212 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 16 May 2009 10:02:05 +0200 Subject: afeb9260: fix macb device init uses PA10, PA11 for ETX2 and ETX3. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 6dc0acc..5309ba2 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -167,7 +167,7 @@ void at91_macb_hw_init(void) at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ -#if defined(CONFIG_AT91SAM9260EK) +#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) /* * use PA10, PA11 for ETX2, ETX3. * PA23 and PA24 are for TWI EEPROM -- cgit v1.1 From 10a451cd57cffbca875c97bbd8929059c5627ec6 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 8 May 2009 20:24:12 +0200 Subject: arm: unify linker script all arm boards except a few use the same cpu linker script so move it to cpu/$(CPU) that could be overwrite in following order SOC BOARD via the corresponding config.mk Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm1136/u-boot.lds | 64 +++++++++++++++++++++++++++++++++++++++ cpu/arm1176/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/arm720t/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/arm920t/u-boot.lds | 64 +++++++++++++++++++++++++++++++++++++++ cpu/arm925t/u-boot.lds | 59 ++++++++++++++++++++++++++++++++++++ cpu/arm926ejs/at91/config.mk | 1 - cpu/arm926ejs/at91/u-boot.lds | 57 ---------------------------------- cpu/arm926ejs/davinci/config.mk | 2 -- cpu/arm926ejs/davinci/u-boot.lds | 52 ------------------------------- cpu/arm926ejs/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/arm946es/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/config.mk | 2 -- cpu/arm_cortexa8/omap3/u-boot.lds | 58 ----------------------------------- cpu/arm_cortexa8/u-boot.lds | 58 +++++++++++++++++++++++++++++++++++ cpu/arm_intcm/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/ixp/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/lh7a40x/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/pxa/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/s3c44b0/u-boot.lds | 56 ++++++++++++++++++++++++++++++++++ cpu/sa1100/u-boot.lds | 59 ++++++++++++++++++++++++++++++++++++ 20 files changed, 808 insertions(+), 172 deletions(-) create mode 100644 cpu/arm1136/u-boot.lds create mode 100644 cpu/arm1176/u-boot.lds create mode 100644 cpu/arm720t/u-boot.lds create mode 100644 cpu/arm920t/u-boot.lds create mode 100644 cpu/arm925t/u-boot.lds delete mode 100644 cpu/arm926ejs/at91/u-boot.lds delete mode 100644 cpu/arm926ejs/davinci/u-boot.lds create mode 100644 cpu/arm926ejs/u-boot.lds create mode 100644 cpu/arm946es/u-boot.lds delete mode 100644 cpu/arm_cortexa8/omap3/u-boot.lds create mode 100644 cpu/arm_cortexa8/u-boot.lds create mode 100644 cpu/arm_intcm/u-boot.lds create mode 100644 cpu/ixp/u-boot.lds create mode 100644 cpu/lh7a40x/u-boot.lds create mode 100644 cpu/pxa/u-boot.lds create mode 100644 cpu/s3c44b0/u-boot.lds create mode 100644 cpu/sa1100/u-boot.lds (limited to 'cpu') diff --git a/cpu/arm1136/u-boot.lds b/cpu/arm1136/u-boot.lds new file mode 100644 index 0000000..7181a56 --- /dev/null +++ b/cpu/arm1136/u-boot.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * Copyright (C) 2005-2007 Samsung Electronics + * Kyungin Park + * + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm1176/u-boot.lds b/cpu/arm1176/u-boot.lds new file mode 100644 index 0000000..cc682f5 --- /dev/null +++ b/cpu/arm1176/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1176/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm720t/u-boot.lds b/cpu/arm720t/u-boot.lds new file mode 100644 index 0000000..111c3f5 --- /dev/null +++ b/cpu/arm720t/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm920t/u-boot.lds b/cpu/arm920t/u-boot.lds new file mode 100644 index 0000000..d9bfbee --- /dev/null +++ b/cpu/arm920t/u-boot.lds @@ -0,0 +1,64 @@ +/* + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * Ming-Len Wu + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm925t/u-boot.lds b/cpu/arm925t/u-boot.lds new file mode 100644 index 0000000..694780e --- /dev/null +++ b/cpu/arm925t/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm926ejs/at91/config.mk b/cpu/arm926ejs/at91/config.mk index 06177e6..19296fd 100644 --- a/cpu/arm926ejs/at91/config.mk +++ b/cpu/arm926ejs/at91/config.mk @@ -1,2 +1 @@ PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) -LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91/u-boot.lds diff --git a/cpu/arm926ejs/at91/u-boot.lds b/cpu/arm926ejs/at91/u-boot.lds deleted file mode 100644 index 8518a1d..0000000 --- a/cpu/arm926ejs/at91/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk index 5221444..a57d03a 100644 --- a/cpu/arm926ejs/davinci/config.mk +++ b/cpu/arm926ejs/davinci/config.mk @@ -33,5 +33,3 @@ PLATFORM_CPPFLAGS += -march=armv5te PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) - -LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/davinci/u-boot.lds diff --git a/cpu/arm926ejs/davinci/u-boot.lds b/cpu/arm926ejs/davinci/u-boot.lds deleted file mode 100644 index e50b8d4..0000000 --- a/cpu/arm926ejs/davinci/u-boot.lds +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm926ejs/u-boot.lds b/cpu/arm926ejs/u-boot.lds new file mode 100644 index 0000000..ee5eeb5 --- /dev/null +++ b/cpu/arm926ejs/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm946es/u-boot.lds b/cpu/arm946es/u-boot.lds new file mode 100644 index 0000000..5bd4390 --- /dev/null +++ b/cpu/arm946es/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm946es/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm_cortexa8/omap3/config.mk b/cpu/arm_cortexa8/omap3/config.mk index 9b028d8..5fbec7a 100644 --- a/cpu/arm_cortexa8/omap3/config.mk +++ b/cpu/arm_cortexa8/omap3/config.mk @@ -34,5 +34,3 @@ PLATFORM_CPPFLAGS +=$(call cc-option) PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ $(call cc-option,-malignment-traps,)) - -LDSCRIPT := $(SRCTREE)/cpu/arm_cortexa8/omap3/u-boot.lds diff --git a/cpu/arm_cortexa8/omap3/u-boot.lds b/cpu/arm_cortexa8/omap3/u-boot.lds deleted file mode 100644 index 4f1711c..0000000 --- a/cpu/arm_cortexa8/omap3/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm_cortexa8/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/cpu/arm_cortexa8/u-boot.lds b/cpu/arm_cortexa8/u-boot.lds new file mode 100644 index 0000000..4f1711c --- /dev/null +++ b/cpu/arm_cortexa8/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm_intcm/u-boot.lds b/cpu/arm_intcm/u-boot.lds new file mode 100644 index 0000000..5eb87fb --- /dev/null +++ b/cpu/arm_intcm/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_intcm/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/ixp/u-boot.lds b/cpu/ixp/u-boot.lds new file mode 100644 index 0000000..85209ca --- /dev/null +++ b/cpu/ixp/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o(.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/lh7a40x/u-boot.lds b/cpu/lh7a40x/u-boot.lds new file mode 100644 index 0000000..e7543c9 --- /dev/null +++ b/cpu/lh7a40x/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/lh7a40x/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/pxa/u-boot.lds b/cpu/pxa/u-boot.lds new file mode 100644 index 0000000..77ab3c9 --- /dev/null +++ b/cpu/pxa/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/s3c44b0/u-boot.lds b/cpu/s3c44b0/u-boot.lds new file mode 100644 index 0000000..41ca3b4 --- /dev/null +++ b/cpu/s3c44b0/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/s3c44b0/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/sa1100/u-boot.lds b/cpu/sa1100/u-boot.lds new file mode 100644 index 0000000..0c02e76 --- /dev/null +++ b/cpu/sa1100/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003-2004 + * MontaVista Software, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} -- cgit v1.1 From c358d9c3f16571e8f825e81b75eaf32e228cb669 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 9 May 2009 13:21:18 +0200 Subject: arm: unify interrupt init all arm init the IRQ stack the same way so unify it in lib_arm/interrupts.c and then call arch specific interrupt init Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm1136/cpu.c | 11 ----------- cpu/arm720t/cpu.c | 7 ------- cpu/arm720t/interrupts.c | 2 +- cpu/arm920t/cpu.c | 11 ----------- cpu/arm925t/cpu.c | 11 ----------- cpu/arm926ejs/cpu.c | 11 ----------- cpu/arm946es/cpu.c | 11 ----------- cpu/arm_cortexa8/cpu.c | 12 ------------ cpu/arm_intcm/cpu.c | 11 ----------- cpu/ixp/cpu.c | 12 ------------ cpu/ixp/interrupts.c | 2 +- cpu/lh7a40x/cpu.c | 11 ----------- cpu/pxa/cpu.c | 11 ----------- cpu/sa1100/cpu.c | 7 ------- 14 files changed, 2 insertions(+), 128 deletions(-) (limited to 'cpu') diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 7381da0..6104f9e 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -35,21 +35,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 6c40903..7a2b9c3 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -42,13 +42,6 @@ static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index ff21314..91d552c 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -111,7 +111,7 @@ static ulong timestamp; static ulong lastdec; #if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B) -int interrupt_init (void) +int arch_interrupt_init (void) { int i; diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index b6ef6bb..e4a8adb 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -33,21 +33,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index 62828b1..e48f341 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -34,21 +34,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 1f70a36..0a32673 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -33,21 +33,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index d3195f9..e0f91d3 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -33,21 +33,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ca6bf4f..b91cc4f 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -36,10 +36,6 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - #ifndef CONFIG_L2_OFF void l2cache_disable(void); #endif @@ -48,14 +44,6 @@ static void cache_flush(void); int cpu_init(void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = - _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index b137f76..488bd0c 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -33,19 +33,8 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 42c62f6..5cfc39d 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -38,10 +38,6 @@ ulong loops_per_jiffy; -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); #if defined(CONFIG_DISPLAY_CPUINFO) @@ -81,14 +77,6 @@ int print_cpuinfo (void) int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; } diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index a05e439..06a826a 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -67,7 +67,7 @@ void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) IRQ_HANDLER[irq].m_func = handle_irq; } -int interrupt_init (void) +int arch_interrupt_init (void) { int i; diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index be92f70..3cf0824 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -33,21 +33,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index 3a1be57..8edb44e 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -35,21 +35,10 @@ #include #include -#ifdef CONFIG_USE_IRQ -DECLARE_GLOBAL_DATA_PTR; -#endif - static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index ed1a6f7..39285a0 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -42,13 +42,6 @@ static void cache_flush(void); int cpu_init (void) { - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif return 0; } -- cgit v1.1 From ad7e8aac6920f8b8a85b3cc2e93bca7458e99aa1 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 9 May 2009 13:21:19 +0200 Subject: arm: remove cpu_init move s3c44b0 to arch_cpu_init and as noone use cpu_init remove it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm1136/cpu.c | 5 ----- cpu/arm1176/cpu.c | 5 ----- cpu/arm720t/cpu.c | 5 ----- cpu/arm920t/cpu.c | 5 ----- cpu/arm925t/cpu.c | 5 ----- cpu/arm926ejs/cpu.c | 5 ----- cpu/arm946es/cpu.c | 5 ----- cpu/arm_cortexa8/cpu.c | 5 ----- cpu/arm_intcm/cpu.c | 5 ----- cpu/ixp/cpu.c | 5 ----- cpu/lh7a40x/cpu.c | 5 ----- cpu/pxa/cpu.c | 5 ----- cpu/s3c44b0/cpu.c | 2 +- cpu/sa1100/cpu.c | 5 ----- 14 files changed, 1 insertion(+), 66 deletions(-) (limited to 'cpu') diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 6104f9e..ade7f46 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -37,11 +37,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index fbc8ea8..c59a77b 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -38,11 +38,6 @@ static void cache_flush (void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 7a2b9c3..88c71bf 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -40,11 +40,6 @@ static void cache_flush(void); #endif -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index e4a8adb..34adb11 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -35,11 +35,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index e48f341..71700bb 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -36,11 +36,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 0a32673..5c902df 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -35,11 +35,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index e0f91d3..c63c98b 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -35,11 +35,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index b91cc4f..6fd07d0 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -42,11 +42,6 @@ void l2cache_disable(void); static void cache_flush(void); -int cpu_init(void) -{ - return 0; -} - int cleanup_before_linux(void) { unsigned int i; diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index 488bd0c..c0748e8 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -33,11 +33,6 @@ #include #include -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 5cfc39d..ce275e5 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -75,11 +75,6 @@ int print_cpuinfo (void) } #endif /* CONFIG_DISPLAY_CPUINFO */ -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 3cf0824..b193189 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -35,11 +35,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index 8edb44e..800d120 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -37,11 +37,6 @@ static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index 7ef4a1f..bca38f8 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -32,7 +32,7 @@ #include #include -int cpu_init (void) +int arch_cpu_init (void) { icache_enable(); diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index 39285a0..58e90dc 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -40,11 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; static void cache_flush(void); -int cpu_init (void) -{ - return 0; -} - int cleanup_before_linux (void) { /* -- cgit v1.1 From 379be585eb2343d8814a5cee5fb3da930d846bee Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 16 May 2009 22:48:46 +0200 Subject: pxa: move serial driver to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/pxa/Makefile | 1 - cpu/pxa/serial.c | 385 ------------------------------------------------------- 2 files changed, 386 deletions(-) delete mode 100644 cpu/pxa/serial.c (limited to 'cpu') diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile index 5dc3a52..07a151a 100644 --- a/cpu/pxa/Makefile +++ b/cpu/pxa/Makefile @@ -30,7 +30,6 @@ START = start.o COBJS += cpu.o COBJS += i2c.o COBJS += pxafb.o -COBJS += serial.o COBJS += timer.o COBJS += usb.o diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c deleted file mode 100644 index 9ba457e..0000000 --- a/cpu/pxa/serial.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define FFUART_INDEX 0 -#define BTUART_INDEX 1 -#define STUART_INDEX 2 - -#ifndef CONFIG_SERIAL_MULTI -#if defined (CONFIG_FFUART) -#define UART_INDEX FFUART_INDEX -#elif defined (CONFIG_BTUART) -#define UART_INDEX BTUART_INDEX -#elif defined (CONFIG_STUART) -#define UART_INDEX STUART_INDEX -#else -#error "Bad: you didn't configure serial ..." -#endif -#endif - -void pxa_setbrg_dev (unsigned int uart_index) -{ - unsigned int quot = 0; - - if (gd->baudrate == 1200) - quot = 768; - else if (gd->baudrate == 9600) - quot = 96; - else if (gd->baudrate == 19200) - quot = 48; - else if (gd->baudrate == 38400) - quot = 24; - else if (gd->baudrate == 57600) - quot = 16; - else if (gd->baudrate == 115200) - quot = 8; - else - hang (); - - switch (uart_index) { - case FFUART_INDEX: -#ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; -#else - CKEN |= CKEN6_FFUART; -#endif /* CONFIG_CPU_MONAHANS */ - - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ - - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; - - FFIER = IER_UUE; /* Enable FFUART */ - break; - - case BTUART_INDEX: -#ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; -#else - CKEN |= CKEN7_BTUART; -#endif /* CONFIG_CPU_MONAHANS */ - - BTIER = 0; - BTFCR = 0; - - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; - - BTIER = IER_UUE; /* Enable BFUART */ - - break; - - case STUART_INDEX: -#ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; -#else - CKEN |= CKEN5_STUART; -#endif /* CONFIG_CPU_MONAHANS */ - - STIER = 0; - STFCR = 0; - - /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; - - STIER = IER_UUE; /* Enable STUART */ - break; - - default: - hang(); - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int pxa_init_dev (unsigned int uart_index) -{ - pxa_setbrg_dev (uart_index); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void pxa_putc_dev (unsigned int uart_index,const char c) -{ - switch (uart_index) { - case FFUART_INDEX: - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; - break; - - case BTUART_INDEX: - while ((BTLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; - break; - - case STUART_INDEX: - while ((STLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; - break; - } - - /* If \n, also do \r */ - if (c == '\n') - pxa_putc_dev (uart_index,'\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_tstc_dev (unsigned int uart_index) -{ - switch (uart_index) { - case FFUART_INDEX: - return FFLSR & LSR_DR; - case BTUART_INDEX: - return BTLSR & LSR_DR; - case STUART_INDEX: - return STLSR & LSR_DR; - } - return -1; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_getc_dev (unsigned int uart_index) -{ - switch (uart_index) { - case FFUART_INDEX: - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; - - case BTUART_INDEX: - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; - case STUART_INDEX: - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; - } - return -1; -} - -void -pxa_puts_dev (unsigned int uart_index,const char *s) -{ - while (*s) { - pxa_putc_dev (uart_index,*s++); - } -} - -#if defined (CONFIG_FFUART) -static int ffuart_init(void) -{ - return pxa_init_dev(FFUART_INDEX); -} - -static void ffuart_setbrg(void) -{ - return pxa_setbrg_dev(FFUART_INDEX); -} - -static void ffuart_putc(const char c) -{ - return pxa_putc_dev(FFUART_INDEX,c); -} - -static void ffuart_puts(const char *s) -{ - return pxa_puts_dev(FFUART_INDEX,s); -} - -static int ffuart_getc(void) -{ - return pxa_getc_dev(FFUART_INDEX); -} - -static int ffuart_tstc(void) -{ - return pxa_tstc_dev(FFUART_INDEX); -} - -struct serial_device serial_ffuart_device = -{ - "serial_ffuart", - "PXA", - ffuart_init, - ffuart_setbrg, - ffuart_getc, - ffuart_tstc, - ffuart_putc, - ffuart_puts, -}; -#endif - -#if defined (CONFIG_BTUART) -static int btuart_init(void) -{ - return pxa_init_dev(BTUART_INDEX); -} - -static void btuart_setbrg(void) -{ - return pxa_setbrg_dev(BTUART_INDEX); -} - -static void btuart_putc(const char c) -{ - return pxa_putc_dev(BTUART_INDEX,c); -} - -static void btuart_puts(const char *s) -{ - return pxa_puts_dev(BTUART_INDEX,s); -} - -static int btuart_getc(void) -{ - return pxa_getc_dev(BTUART_INDEX); -} - -static int btuart_tstc(void) -{ - return pxa_tstc_dev(BTUART_INDEX); -} - -struct serial_device serial_btuart_device = -{ - "serial_btuart", - "PXA", - btuart_init, - btuart_setbrg, - btuart_getc, - btuart_tstc, - btuart_putc, - btuart_puts, -}; -#endif - -#if defined (CONFIG_STUART) -static int stuart_init(void) -{ - return pxa_init_dev(STUART_INDEX); -} - -static void stuart_setbrg(void) -{ - return pxa_setbrg_dev(STUART_INDEX); -} - -static void stuart_putc(const char c) -{ - return pxa_putc_dev(STUART_INDEX,c); -} - -static void stuart_puts(const char *s) -{ - return pxa_puts_dev(STUART_INDEX,s); -} - -static int stuart_getc(void) -{ - return pxa_getc_dev(STUART_INDEX); -} - -static int stuart_tstc(void) -{ - return pxa_tstc_dev(STUART_INDEX); -} - -struct serial_device serial_stuart_device = -{ - "serial_stuart", - "PXA", - stuart_init, - stuart_setbrg, - stuart_getc, - stuart_tstc, - stuart_putc, - stuart_puts, -}; -#endif - - -#ifndef CONFIG_SERIAL_MULTI -inline int serial_init(void) { - return (pxa_init_dev(UART_INDEX)); -} -void serial_setbrg(void) { - pxa_setbrg_dev(UART_INDEX); -} -int serial_getc(void) { - return(pxa_getc_dev(UART_INDEX)); -} -int serial_tstc(void) { - return(pxa_tstc_dev(UART_INDEX)); -} -void serial_putc(const char c) { - pxa_putc_dev(UART_INDEX,c); -} -void serial_puts(const char *s) { - pxa_puts_dev(UART_INDEX,s); -} -#endif /* CONFIG_SERIAL_MULTI */ -- cgit v1.1 From 3ea201b016ab259a5ac8824af767569522768c47 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 31 May 2009 12:44:27 +0200 Subject: lh7a40x: move serial driver to drivers/serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/lh7a40x/Makefile | 2 +- cpu/lh7a40x/serial.c | 184 --------------------------------------------------- 2 files changed, 1 insertion(+), 185 deletions(-) delete mode 100644 cpu/lh7a40x/serial.c (limited to 'cpu') diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile index b9ae76e..1b3f58a 100644 --- a/cpu/lh7a40x/Makefile +++ b/cpu/lh7a40x/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = cpu.o speed.o serial.o timer.o +COBJS = cpu.o speed.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c deleted file mode 100644 index 4767489..0000000 --- a/cpu/lh7a40x/serial.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONSOLE_UART1) -# define UART_CONSOLE 1 -#elif defined(CONFIG_CONSOLE_UART2) -# define UART_CONSOLE 2 -#elif defined(CONFIG_CONSOLE_UART3) -# define UART_CONSOLE 3 -#else -# error "No console configured ... " -#endif - -void serial_setbrg (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - int i; - unsigned int reg = 0; - - /* - * userguide 15.1.2.4 - * - * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1 - * - * UART_REF_FREQ = external system clock input / 2 (Hz) - * BAUD is desired baudrate (bits/s) - * - * NOTE: we add (divisor/2) to numerator to round for - * more precision - */ - reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1; - uart->brcon = reg; - - for (i = 0; i < 100; i++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* UART must be enabled before writing to any config registers */ - uart->con |= (UART_EN); - -#ifdef CONFIG_CONSOLE_UART1 - /* infrared disabled */ - uart->con |= UART_SIRD; -#endif - /* loopback disabled */ - uart->con &= ~(UART_LBE); - - /* modem lines and tx/rx polarities */ - uart->con &= ~(UART_MXP | UART_TXP | UART_RXP); - - /* FIFO enable, N81 */ - uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1); - - /* set baudrate */ - serial_setbrg (); - - /* enable rx interrupt */ - uart->inten |= UART_RI; - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* wait for character to arrive */ - while (uart->status & UART_RXFE); - - return(uart->data & 0xff); -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->status & UART_TXFE)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->status & UART_CTS)); -#endif - - uart->data = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - return(!(uart->status & UART_RXFE)); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} -- cgit v1.1 From 61cf851b09cf8b67009ec11fc47c16add6b142a5 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 31 May 2009 12:44:43 +0200 Subject: omap24xx: rename reset file Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm1136/omap24xx/Makefile | 2 +- cpu/arm1136/omap24xx/reset.S | 42 ++++++++++++++++++++++++++++++++++++++++++ cpu/arm1136/omap24xx/start.S | 42 ------------------------------------------ 3 files changed, 43 insertions(+), 43 deletions(-) create mode 100644 cpu/arm1136/omap24xx/reset.S delete mode 100644 cpu/arm1136/omap24xx/start.S (limited to 'cpu') diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile index 2a79d9b..48dc7e3 100644 --- a/cpu/arm1136/omap24xx/Makefile +++ b/cpu/arm1136/omap24xx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -SOBJS = start.o +SOBJS = reset.o COBJS = timer.o diff --git a/cpu/arm1136/omap24xx/reset.S b/cpu/arm1136/omap24xx/reset.S new file mode 100644 index 0000000..5f8343f --- /dev/null +++ b/cpu/arm1136/omap24xx/reset.S @@ -0,0 +1,42 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl reset_cpu +reset_cpu: + ldr r1, rstctl /* get addr for global reset reg */ + mov r3, #0x2 /* full reset pll+mpu */ + str r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PM_RSTCTRL_WKUP diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/start.S deleted file mode 100644 index 5f8343f..0000000 --- a/cpu/arm1136/omap24xx/start.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP -- cgit v1.1 From 5bb59b3c906ee01adfaac9565443e5236a793079 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 31 May 2009 12:44:45 +0200 Subject: at91: extract reset from timer Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm926ejs/at91/Makefile | 1 + cpu/arm926ejs/at91/reset.c | 42 ++++++++++++++++++++++++++++++++++++++++++ cpu/arm926ejs/at91/timer.c | 15 --------------- 3 files changed, 43 insertions(+), 15 deletions(-) create mode 100644 cpu/arm926ejs/at91/reset.c (limited to 'cpu') diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 71acb0b..66eec76 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o +COBJS-y += reset.o COBJS-y += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c new file mode 100644 index 0000000..f963e14 --- /dev/null +++ b/cpu/arm926ejs/at91/reset.c @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * Reset the cpu by setting up the watchdog timer and let him time out. + */ +void reset_cpu(ulong ignored) +{ + /* this is the way Linux does it */ + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_PERRST); + + while (1); + /* Never reached */ +} diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index c84cb5e..811bb3c 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -139,17 +138,3 @@ ulong get_tbclk(void) tbclk = CONFIG_SYS_HZ; return tbclk; } - -/* - * Reset the cpu by setting up the watchdog timer and let him time out. - */ -void reset_cpu(ulong ignored) -{ - /* this is the way Linux does it */ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | - AT91_RSTC_PROCRST | - AT91_RSTC_PERRST); - - while (1); - /* Never reached */ -} -- cgit v1.1 From b2403589b4d9996394bafc73eca3623f43ac2c31 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 31 May 2009 14:53:18 +0200 Subject: at91: move cpu info print to cpu Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm926ejs/at91/cpu.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index 2ae97fe..f2f7b62 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -21,17 +21,34 @@ * MA 02111-1307 USA */ -#include +#include #include #include #include #include +#ifndef AT91_MAIN_CLOCK +#define AT91_MAIN_CLOCK 0 +#endif + int arch_cpu_init(void) { -#ifdef AT91_MAIN_CLOCK return at91_clock_init(AT91_MAIN_CLOCK); -#else - return at91_clock_init(0); -#endif } + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU: %s\n", AT91_CPU_NAME); + printf("Crystal frequency: %8s MHz\n", + strmhz(buf, get_main_clk_rate())); + printf("CPU clock : %8s MHz\n", + strmhz(buf, get_cpu_clk_rate())); + printf("Master clock : %8s MHz\n", + strmhz(buf, get_mck_clk_rate())); + + return 0; +} +#endif -- cgit v1.1 From 708cfb74b7c6df9c37d3c48988a154be79daefeb Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Fri, 29 May 2009 18:57:31 -0500 Subject: OMAP3 Turn on the GPIO bank clocks The function and interface clocks for each GPIO bank, except the first, must be explicitly turned on. These are controlled by the config level defines CONFIG_OMAP3_GPIO_n where n is from 2 to 6. Signed-off-by: Tom Rix Acked-by: Dirk Behme --- cpu/arm_cortexa8/omap3/clock.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index d035677..0306b6c 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -357,6 +357,28 @@ void per_clocks_enable(void) sr32(&prcm_base->fclken_per, 11, 1, 0x1); sr32(&prcm_base->iclken_per, 11, 1, 0x1); #endif + +#ifdef CONFIG_OMAP3_GPIO_2 + sr32(&prcm_base->fclken_per, 13, 1, 1); + sr32(&prcm_base->iclken_per, 13, 1, 1); +#endif +#ifdef CONFIG_OMAP3_GPIO_3 + sr32(&prcm_base->fclken_per, 14, 1, 1); + sr32(&prcm_base->iclken_per, 14, 1, 1); +#endif +#ifdef CONFIG_OMAP3_GPIO_4 + sr32(&prcm_base->fclken_per, 15, 1, 1); + sr32(&prcm_base->iclken_per, 15, 1, 1); +#endif +#ifdef CONFIG_OMAP3_GPIO_5 + sr32(&prcm_base->fclken_per, 16, 1, 1); + sr32(&prcm_base->iclken_per, 16, 1, 1); +#endif +#ifdef CONFIG_OMAP3_GPIO_6 + sr32(&prcm_base->fclken_per, 17, 1, 1); + sr32(&prcm_base->iclken_per, 17, 1, 1); +#endif + #ifdef CONFIG_DRIVER_OMAP34XX_I2C /* Turn on all 3 I2C clocks */ sr32(&prcm_base->fclken1_core, 15, 3, 0x7); -- cgit v1.1 From ecb1dc892297d5d99876907328fed732feefeab2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 20 May 2009 04:35:14 -0400 Subject: Add support for Linux-like kallsysms The kernel stores address<->symbol names in it so things can be decoded at runtime. Do it in U-Boot, and we get nice symbol decoding when crashing. Signed-off-by: Mike Frysinger --- cpu/blackfin/system_map.S | 18 ------------------ cpu/blackfin/traps.c | 35 +++++------------------------------ 2 files changed, 5 insertions(+), 48 deletions(-) delete mode 100644 cpu/blackfin/system_map.S (limited to 'cpu') diff --git a/cpu/blackfin/system_map.S b/cpu/blackfin/system_map.S deleted file mode 100644 index 286d7f3..0000000 --- a/cpu/blackfin/system_map.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * system_map.S - optional symbol lookup for debugging - * - * Copyright (c) 2007 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include - -#ifdef CONFIG_DEBUG_DUMP_SYMS -.data -.global _system_map -.type _system_map,@object -_system_map: -#include SYM_FILE -.asciz "" -.size _system_map,.-_system_map -#endif diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index 2121b0e..7e7c74c 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -171,38 +171,13 @@ void trap_c(struct pt_regs *regs) # define ENABLE_DUMP 0 #endif -#ifdef CONFIG_DEBUG_DUMP_SYMS -# define ENABLE_DUMP_SYMS 1 -#else -# define ENABLE_DUMP_SYMS 0 -#endif - -static const char *symbol_lookup(unsigned long addr, unsigned long *caddr) +#ifndef CONFIG_KALLSYMS +const char *symbol_lookup(unsigned long addr, unsigned long *caddr) { - if (!ENABLE_DUMP_SYMS) - return NULL; - - extern const char system_map[] __attribute__((__weak__)); - const char *sym, *csym; - char *esym; - unsigned long sym_addr; - - sym = system_map; - csym = NULL; - *caddr = 0; - - while (*sym) { - sym_addr = simple_strtoul(sym, &esym, 16); - sym = esym; - if (sym_addr > addr) - break; - *caddr = sym_addr; - csym = sym; - sym += strlen(sym) + 1; - } - - return csym; + *caddr = addr; + return "N/A"; } +#endif static void decode_address(char *buf, unsigned long address) { -- cgit v1.1 From a89c33db96a1e55319a286dd4c3c05ca64ac6bfd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 24 May 2009 17:06:54 +0200 Subject: General help message cleanup Many of the help messages were not really helpful; for example, many commands that take no arguments would not print a correct synopsis line, but "No additional help available." which is not exactly wrong, but not helpful either. Commit ``Make "usage" messages more helpful.'' changed this partially. But it also became clear that lots of "Usage" and "Help" messages (fields "usage" and "help" in struct cmd_tbl_s respective) were actually redundant. This patch cleans this up - for example: Before: => help dtt dtt - Digital Thermometer and Thermostat Usage: dtt - Read temperature from digital thermometer and thermostat. After: => help dtt dtt - Read temperature from Digital Thermometer and Thermostat Usage: dtt Signed-off-by: Wolfgang Denk --- cpu/arm_cortexa8/omap3/board.c | 4 ++-- cpu/mpc512x/iim.c | 4 ++-- cpu/mpc512x/speed.c | 2 +- cpu/mpc83xx/speed.c | 2 +- cpu/nios/asmi.c | 2 +- cpu/nios2/epcs.c | 2 +- cpu/nios2/sysid.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..6e29599 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -335,8 +335,8 @@ usage: U_BOOT_CMD( nandecc, 2, 1, do_switch_ecc, "nandecc - switch OMAP3 NAND ECC calculation algorithm\n", - "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n" - ); + "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" +); #endif /* CONFIG_NAND_OMAP_GPMC */ diff --git a/cpu/mpc512x/iim.c b/cpu/mpc512x/iim.c index 6cdc422..8f2eb37 100644 --- a/cpu/mpc512x/iim.c +++ b/cpu/mpc512x/iim.c @@ -389,6 +389,6 @@ U_BOOT_CMD( " no args for entire bank\n" "fuse prog - program fuse at row , bit <_bit>\n" " is 0-31, is 0-7; eg. 13_2 \n" - " WARNING - this is permanent\n" - ); + " WARNING - this is permanent" +); #endif /* CONFIG_CMD_FUSE */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 5992111..1f90862 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -138,7 +138,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(clocks, 1, 0, do_clocks, "print clock configuration", - " clocks\n" + " clocks" ); int prt_mpc512x_clks (void) diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 9b7e7b5..95b558f 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -545,5 +545,5 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(clocks, 1, 0, do_clocks, "print clock configuration", - " clocks\n" + " clocks" ); diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c index 2c2e838..33553b7 100644 --- a/cpu/nios/asmi.c +++ b/cpu/nios/asmi.c @@ -48,7 +48,7 @@ "asmi write addr offset count\n"\ " - write count bytes to offset from addr.\n"\ "asmi verify addr offset count\n"\ - " - verify count bytes at offset from addr.\n" + " - verify count bytes at offset from addr." /*-----------------------------------------------------------------------*/ diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c index 968b50f..483b249 100644 --- a/cpu/nios2/epcs.c +++ b/cpu/nios2/epcs.c @@ -47,7 +47,7 @@ "epcs write addr offset count\n"\ " - write count bytes to offset from addr.\n"\ "epcs verify addr offset count\n"\ - " - verify count bytes at offset from addr.\n" + " - verify count bytes at offset from addr." /*-----------------------------------------------------------------------*/ diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index 251204b..77bc8b5 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -53,6 +53,6 @@ int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sysid, 1, 1, do_sysid, "display Nios-II system id", - "\n - display Nios-II system id\n" + "" ); #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ -- cgit v1.1 From 03e069dc0a765d506f78a68319acf33d432e035b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:37 +0200 Subject: mpc512x: change cpu/mpc512x/Makefile to use Kconfig style Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index 297d135..d6bfd59 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2007 DENX Software Engineering +# (C) Copyright 2007-2009 DENX Software Engineering # # See file CREDITS for list of people who contributed to this # project. @@ -25,11 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o -ifdef CONFIG_IIM -COBJS += iim.o -endif +COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o +COBJS-${CONFIG_IIM} += iim.o +COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) -- cgit v1.1 From de26ef99bddbce4ed225f93afcf0bee99c3b6f87 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:38 +0200 Subject: mpc512x: Move common files to share them by several boards We will soon see several new MPC521x based boards added. This patch moves files that are not board specific to a common directory so they can be shared by all such ports. It also splits off common IDE code into a new file, cpu/mpc512x/ide.c . Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/Makefile | 7 ++ cpu/mpc512x/config.mk | 6 +- cpu/mpc512x/diu.c | 189 +++++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/ide.c | 128 +++++++++++++++++++++++++++++ cpu/mpc512x/pci.c | 213 +++++++++++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/u-boot.lds | 121 ++++++++++++++++++++++++++++ 6 files changed, 663 insertions(+), 1 deletion(-) create mode 100644 cpu/mpc512x/diu.c create mode 100644 cpu/mpc512x/ide.c create mode 100644 cpu/mpc512x/pci.c create mode 100644 cpu/mpc512x/u-boot.lds (limited to 'cpu') diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index d6bfd59..022c676 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -22,11 +22,18 @@ include $(TOPDIR)/config.mk +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + LIB = $(obj)lib$(CPU).a START = start.o COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o +COBJS-${CONFIG_FSL_DIU_FB} += diu.o +COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o +COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o +COBJS-${CONFIG_CMD_IDE} += ide.o COBJS-${CONFIG_IIM} += iim.o +COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 5b7e1f2..6ab34b1 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2007 DENX Software Engineering +# (C) Copyright 2007-2009 DENX Software Engineering # # See file CREDITS for list of people who contributed to this # project. @@ -23,3 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -msoft-float -mcpu=603e + +# Use default linker script. +# A board port can override this setting in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c new file mode 100644 index 0000000..6d7e40f --- /dev/null +++ b/cpu/mpc512x/diu.c @@ -0,0 +1,189 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * York Sun + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "../../board/freescale/common/pixis.h" +#include "../../board/freescale/common/fsl_diu_fb.h" + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include +#include +#endif + +#ifdef CONFIG_FSL_DIU_LOGO_BMP +extern unsigned int FSL_Logo_BMP[]; +#else +#define FSL_Logo_BMP NULL +#endif + +static int xres, yres; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile clk512x_t *clk = &immap->clk; + volatile unsigned int *clkdvdr = &clk->scfr[0]; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0) * 4; + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr); + temp = *clkdvdr & 0xFFFFFF00; + *clkdvdr = temp | (pixval & 0xFF); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); +} + +char *valid_bmp(char *addr) +{ + unsigned long h_addr; + + h_addr = simple_strtoul(addr, NULL, 16); + if (h_addr < CONFIG_SYS_FLASH_BASE || + h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { + printf("bmp addr %lx is not a valid flash address\n", h_addr); + return 0; + } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { + printf("bmp addr is not a bmp\n"); + return 0; + } else + return (char *)h_addr; +} + +int mpc5121_diu_init(void) +{ + unsigned int pixel_format; + char *bmp = NULL; + char *bmp_env; + + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + + debug("mpc5121_diu_init\n"); + bmp_env = getenv("diu_bmp_addr"); + if (bmp_env) { + bmp = valid_bmp(bmp_env); + } + if (!bmp) + bmp = FSL_Logo_BMP; + return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); +} + +int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + unsigned int addr; + + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + + if (!strncmp(argv[1], "init", 4)) { +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + fsl_diu_clear_screen(); + drv_video_init(); +#else + return mpc5121_diu_init(); +#endif + } else { + addr = simple_strtoul(argv[1], NULL, 16); + fsl_diu_clear_screen(); + fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); + } + + return 0; +} + +U_BOOT_CMD( + diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp, + "Init or Display BMP file", + "init\n - initialize DIU\n" + "addr\n - display bmp at address 'addr'" + ); + + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + +/* + * The Graphic Device + */ +GraphicDevice ctfb; +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) &ctfb; + struct fb_info *info; + + if (mpc5121_diu_init() < 0) + return; + + /* fill in Graphic device struct */ + sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", + xres, yres, 32, 64, 60); + + pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); + pGD->winSizeX = xres; + pGD->winSizeY = yres - info->logo_height; + pGD->plnSizeX = pGD->winSizeX; + pGD->plnSizeY = pGD->winSizeY; + + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + + pGD->isaBase = 0; + pGD->pciBase = 0; + pGD->memSize = info->screen_size - info->logo_size; + + /* Cursor Start Address */ + pGD->dprBase = 0; + pGD->vprBase = 0; + pGD->cprBase = 0; + + return (void *)pGD; +} + +/** + * Set the LUT + * + * @index: color number + * @r: red + * @b: blue + * @g: green + */ +void video_set_lut + (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + return; +} + +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/cpu/mpc512x/ide.c b/cpu/mpc512x/ide.c new file mode 100644 index 0000000..16f1a01 --- /dev/null +++ b/cpu/mpc512x/ide.c @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2007-2009 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + debug ("init_ide_reset\n"); + + /* + * Clear the reset bit to reset the interface + * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus + */ + immr->pata.pata_ata_control = 0; + udelay(100); + /* Assert the reset bit to enable the interface */ + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + udelay(100); +} + +void ide_set_reset (int idereset) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + debug ("ide_set_reset(%d)\n", idereset); + + if (idereset) { + immr->pata.pata_ata_control = 0; + udelay(100); + } else { + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + udelay(100); + } +} + +#define CALC_TIMING(t) (t + period - 1) / period + +int ide_preinit (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + long t; + const struct { + short t0; + short t1; + short t2_8; + short t2_16; + short t2i; + short t4; + short t9; + short tA; + } pio_specs = { + .t0 = 600, + .t1 = 70, + .t2_8 = 290, + .t2_16 = 165, + .t2i = 0, + .t4 = 30, + .t9 = 20, + .tA = 50, + }; + union { + u32 config; + struct { + u8 field1; + u8 field2; + u8 field3; + u8 field4; + }bytes; + }cfg; + + debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n", + (u32)&immr->pata); + + /* Set the reset bit to 1 to enable the interface */ + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + + /* Init timings : we use PIO mode 0 timings */ + t = 1000000000 / gd->ips_clk; /* period in ns */ + cfg.bytes.field1 = 3; + cfg.bytes.field2 = 3; + cfg.bytes.field3 = (pio_specs.t1 + t) / t; + cfg.bytes.field4 = (pio_specs.t2_8 + t) / t; + + immr->pata.pata_time1 = cfg.config; + + cfg.bytes.field1 = (pio_specs.t2_8 + t) / t; + cfg.bytes.field2 = (pio_specs.tA + t) / t + 2; + cfg.bytes.field3 = 1; + cfg.bytes.field4 = (pio_specs.t4 + t) / t; + + immr->pata.pata_time2 = cfg.config; + + cfg.config = immr->pata.pata_time3; + cfg.bytes.field1 = (pio_specs.t9 + t) / t; + + immr->pata.pata_time3 = cfg.config; + debug ("PATA preinit complete.\n"); + + return 0; +} + +#endif /* defined(CONFIG_IDE_RESET) */ diff --git a/cpu/mpc512x/pci.c b/cpu/mpc512x/pci.c new file mode 100644 index 0000000..806c428 --- /dev/null +++ b/cpu/mpc512x/pci.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include +#include +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE + +static struct pci_controller pci_hose; + + +/************************************************************************** + * pci_init_board() + * + */ +void +pci_init_board(void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile law512x_t *pci_law; + volatile pot512x_t *pci_pot; + volatile pcictrl512x_t *pci_ctrl; + volatile pciconf512x_t *pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller *hose; + + /* Set PCI divider for 33MHz */ + reg32 = immr->clk.scfr[0]; + reg32 &= ~(SCFR1_PCI_DIV_MASK); + reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT; + immr->clk.scfr[0] = reg32; + + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = &immr->pci_ctrl; + pci_conf = &immr->pci_conf; + + hose = &pci_hose; + + /* + * Release PCI RST Output signal + */ + pci_ctrl->gcr = 0; + udelay(2000); + pci_ctrl->gcr = 1; + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; i++) + udelay(1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M; + + /* PCI IO space */ + pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; + + /* PCI mmio - non-prefetch mem space */ + pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, + CONFIG_SYS_PCI_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CONFIG_SYS_IMMR + 0x8300), + (CONFIG_SYS_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} + +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int tmp[2]; + const char *path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose.first_busno); + tmp[1] = cpu_to_be32(pci_hose.last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } + } +} +#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc512x/u-boot.lds b/cpu/mpc512x/u-boot.lds new file mode 100644 index 0000000..dae3269 --- /dev/null +++ b/cpu/mpc512x/u-boot.lds @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) -- cgit v1.1 From 8b251263191ec554967dd1add6237c1ba7f7eb25 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:39 +0200 Subject: cpu/mpc512x/pci.c: minor coding style cleanup Get rid of variable declaration in the middle of the code. Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/pci.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/pci.c b/cpu/mpc512x/pci.c index 806c428..3c63592 100644 --- a/cpu/mpc512x/pci.c +++ b/cpu/mpc512x/pci.c @@ -54,6 +54,7 @@ pci_init_board(void) u16 reg16; u32 reg32; u32 dev; + int i; struct pci_controller *hose; /* Set PCI divider for 33MHz */ @@ -77,12 +78,8 @@ pci_init_board(void) pci_ctrl->gcr = 1; /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; i++) - udelay(1000); - } + for (i = 0; i < 1000; i++) + udelay(1000); /* * Configure PCI Local Access Windows -- cgit v1.1 From debf87415579c0f50aab9e0832976d4506babe0f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:40 +0200 Subject: cpu/mpc512x/diu.c: fix warning: assignment from incompatible pointer type Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/diu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c index 6d7e40f..70849ee 100644 --- a/cpu/mpc512x/diu.c +++ b/cpu/mpc512x/diu.c @@ -95,7 +95,7 @@ int mpc5121_diu_init(void) bmp = valid_bmp(bmp_env); } if (!bmp) - bmp = FSL_Logo_BMP; + bmp = (char *)FSL_Logo_BMP; return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); } -- cgit v1.1 From 19dc7e179268be148e550c36203208c662610d76 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:42 +0200 Subject: MPC512x: add more hardware description to immap_512x.h - add GPIO module description - add Address Latch Timing Register description - add IO Control Memory Map - add FEC Memory Map Also change board/freescale/mpc5121ads/mpc5121ads.c and cpu/mpc512x/iopin.c as needed. Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/iopin.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index 78f4fa1e..befa586 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -23,15 +23,15 @@ #include #include -#include +#include void iopin_initialize(iopin_t *ioregs_init, int len) { short i, j, p; - u_long *reg; + u32 *reg; immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - reg = (u_long *)&(im->io_ctrl.regs[0]); + reg = (u32 *)&(im->io_ctrl); if (sizeof(ioregs_init) == 0) return; -- cgit v1.1 From 843efb1192cc8fd4f904a23dbab4e0fe3e1c5bc2 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:43 +0200 Subject: MPC512x: use I/O accessors instead of pointer accesses This commit changes the MPC512x code to use I/O accessor calls (i.e. out_*() and in_*()) instead of using deprecated pointer accesses. Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/cpu_init.c | 26 +++++++++++------- cpu/mpc512x/i2c.c | 56 +++++++++++++++++++++------------------ cpu/mpc512x/ide.c | 52 ++++++++++++++++++------------------ cpu/mpc512x/iopin.c | 6 ++--- cpu/mpc512x/pci.c | 71 +++++++++++++++++++++++++++++++------------------- cpu/mpc512x/serial.c | 64 +++++++++++++++++++++++---------------------- cpu/mpc512x/speed.c | 23 +++++++++++----- 7 files changed, 168 insertions(+), 130 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c index fa753c8..69ec871 100644 --- a/cpu/mpc512x/cpu_init.c +++ b/cpu/mpc512x/cpu_init.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. - * (C) Copyright 2007 DENX Software Engineering + * Copyright (C) 2007-2009 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -26,6 +26,8 @@ #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -46,30 +48,34 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + out_be32(&im->arbiter.acr, + (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) + ); #endif #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); + out_be32(im->arbiter.acr, + (im->arbiter.acr & ~(ACR_RPTCNT)) | + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) + ); #endif /* RSR - Reset Status Register - clear all status */ gd->reset_status = im->reset.rsr; - im->reset.rsr = ~(RSR_RES); + out_be32(&im->reset.rsr, ~RSR_RES); /* * RMR - Reset Mode Register - enable checkstop reset */ - im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT)); + out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT)); /* Set IPS-CSB divider: IPS = 1/2 CSB */ - ips_div = im->clk.scfr[0]; + ips_div = in_be32(&im->clk.scfr[0]); ips_div &= ~(SCFR1_IPS_DIV_MASK); ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; - im->clk.scfr[0] = ips_div; + out_be32(&im->clk.scfr[0], ips_div); /* * Enable Time Base/Decrementer @@ -78,7 +84,7 @@ void cpu_init_f (volatile immap_t * im) * have udelay() working; if not enabled, usually leads to a hang, like * during FLASH chip identification etc. */ - im->sysconf.spcr |= SPCR_TBEN; + setbits_be32(&im->sysconf.spcr, SPCR_TBEN); } int cpu_init_r (void) diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 0da906a..4a3f9a0 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003 - 2007 + * (C) Copyright 2003 - 2009 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -24,6 +24,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,8 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -#define immr ((immap_t *)CONFIG_SYS_IMMR) - /* by default set I2C bus 0 active */ static unsigned int bus_num = 0; @@ -56,29 +55,24 @@ static int mpc_get_fdr(int); static int mpc_reg_in (volatile u32 *reg) { - int ret = *reg >> 24; - __asm__ __volatile__ ("eieio"); + int ret = in_be32(reg) >> 24; + return ret; } static void mpc_reg_out (volatile u32 *reg, int val, int mask) { - int tmp; - if (!mask) { - *reg = val << 24; + out_be32(reg, val << 24); } else { - tmp = mpc_reg_in (reg); - *reg = ((tmp & ~mask) | (val & mask)) << 24; + clrsetbits_be32(reg, mask << 24, (val & mask) << 24); } - __asm__ __volatile__ ("eieio"); - - return; } static int wait_for_bb (void) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int timeout = I2C_TIMEOUT; int status; @@ -101,7 +95,8 @@ static int wait_for_bb (void) static int wait_for_pin (int *status) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int timeout = I2C_TIMEOUT; *status = mpc_reg_in (®s->msr); @@ -122,7 +117,8 @@ static int wait_for_pin (int *status) static int do_address (uchar chip, char rdwr_flag) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int status; chip <<= 1; @@ -147,7 +143,8 @@ static int do_address (uchar chip, char rdwr_flag) static int send_bytes (uchar chip, char *buf, int len) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int wrcount; int status; @@ -170,7 +167,8 @@ static int send_bytes (uchar chip, char *buf, int len) static int receive_bytes (uchar chip, char *buf, int len) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int dummy = 1; int rdcount = 0; int status; @@ -208,9 +206,12 @@ static int receive_bytes (uchar chip, char *buf, int len) void i2c_init (int speed, int saddr) { + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; int i; - for(i = 0; i < I2C_BUS_CNT; i++){ - i2c512x_dev_t *regs = &immr->i2c.dev[i]; + + for (i = 0; i < I2C_BUS_CNT; i++){ + volatile i2c512x_dev_t *regs = &im->i2c.dev[i]; + mpc_reg_out (®s->mcr, 0, 0); /* Set clock */ @@ -223,10 +224,10 @@ void i2c_init (int speed, int saddr) } /* Disable interrupts */ - immr->i2c.icr = 0; + out_be32(&im->i2c.icr, 0); + /* Turn off filters */ - immr->i2c.mifr = 0; - return; + out_be32(&im->i2c.mifr, 0); } static int mpc_get_fdr (int speed) @@ -281,7 +282,8 @@ static int mpc_get_fdr (int speed) int i2c_probe (uchar chip) { - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; int i; for (i = 0; i < I2C_RETRIES; i++) { @@ -302,8 +304,9 @@ int i2c_probe (uchar chip) int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) { + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; char xaddr[4]; - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; int ret = -1; xaddr[0] = (addr >> 24) & 0xFF; @@ -346,8 +349,9 @@ Done: int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) { + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; char xaddr[4]; - i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; int ret = -1; xaddr[0] = (addr >> 24) & 0xFF; diff --git a/cpu/mpc512x/ide.c b/cpu/mpc512x/ide.c index 16f1a01..dd6b2f4 100644 --- a/cpu/mpc512x/ide.c +++ b/cpu/mpc512x/ide.c @@ -23,47 +23,46 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_IDE_RESET) +void ide_set_reset (int idereset) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + debug ("ide_set_reset(%d)\n", idereset); + + if (idereset) { + out_be32(&im->pata.pata_ata_control, 0); + } else { + out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B); + } + udelay(100); +} + void init_ide_reset (void) { - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; debug ("init_ide_reset\n"); /* * Clear the reset bit to reset the interface * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus */ - immr->pata.pata_ata_control = 0; - udelay(100); - /* Assert the reset bit to enable the interface */ - immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; - udelay(100); -} + ide_set_reset(1); -void ide_set_reset (int idereset) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - debug ("ide_set_reset(%d)\n", idereset); + /* Assert the reset bit to enable the interface */ + ide_set_reset(0); - if (idereset) { - immr->pata.pata_ata_control = 0; - udelay(100); - } else { - immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; - udelay(100); - } } #define CALC_TIMING(t) (t + period - 1) / period int ide_preinit (void) { - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; long t; const struct { short t0; @@ -92,13 +91,13 @@ int ide_preinit (void) u8 field3; u8 field4; }bytes; - }cfg; + } cfg; debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n", - (u32)&immr->pata); + (u32)&im->pata); /* Set the reset bit to 1 to enable the interface */ - immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + ide_set_reset(0); /* Init timings : we use PIO mode 0 timings */ t = 1000000000 / gd->ips_clk; /* period in ns */ @@ -107,19 +106,20 @@ int ide_preinit (void) cfg.bytes.field3 = (pio_specs.t1 + t) / t; cfg.bytes.field4 = (pio_specs.t2_8 + t) / t; - immr->pata.pata_time1 = cfg.config; + out_be32(&im->pata.pata_time1, cfg.config); cfg.bytes.field1 = (pio_specs.t2_8 + t) / t; cfg.bytes.field2 = (pio_specs.tA + t) / t + 2; cfg.bytes.field3 = 1; cfg.bytes.field4 = (pio_specs.t4 + t) / t; - immr->pata.pata_time2 = cfg.config; + out_be32(&im->pata.pata_time2, cfg.config); - cfg.config = immr->pata.pata_time3; + cfg.config = in_be32(&im->pata.pata_time3); cfg.bytes.field1 = (pio_specs.t9 + t) / t; - immr->pata.pata_time3 = cfg.config; + out_be32(&im->pata.pata_time3, cfg.config); + debug ("PATA preinit complete.\n"); return 0; diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index befa586..be20947 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -23,7 +23,7 @@ #include #include -#include +#include void iopin_initialize(iopin_t *ioregs_init, int len) { @@ -40,9 +40,9 @@ void iopin_initialize(iopin_t *ioregs_init, int len) for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); p < ioregs_init[i].nr_pins; p++, j++) { if (ioregs_init[i].bit_or) - reg[j] |= ioregs_init[i].val; + setbits_be32(reg + j, ioregs_init[i].val); else - reg[j] = ioregs_init[i].val; + out_be32 (reg + j, ioregs_init[i].val); } } return; diff --git a/cpu/mpc512x/pci.c b/cpu/mpc512x/pci.c index 3c63592..166a993 100644 --- a/cpu/mpc512x/pci.c +++ b/cpu/mpc512x/pci.c @@ -1,5 +1,6 @@ /* * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved. + * Copyright (C) 2009 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -22,6 +23,7 @@ #include +#include #include #include #include @@ -46,7 +48,7 @@ static struct pci_controller pci_hose; void pci_init_board(void) { - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile law512x_t *pci_law; volatile pot512x_t *pci_pot; volatile pcictrl512x_t *pci_ctrl; @@ -58,24 +60,29 @@ pci_init_board(void) struct pci_controller *hose; /* Set PCI divider for 33MHz */ - reg32 = immr->clk.scfr[0]; + reg32 = im->clk.scfr[0]; reg32 &= ~(SCFR1_PCI_DIV_MASK); reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT; - immr->clk.scfr[0] = reg32; + im->clk.scfr[0] = reg32; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = &immr->pci_ctrl; - pci_conf = &immr->pci_conf; + clrsetbits_be32(&im->clk.scfr[0], + SCFR1_PCI_DIV_MASK, + SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT + ); + + pci_law = im->sysconf.pcilaw; + pci_pot = im->ios.pot; + pci_ctrl = &im->pci_ctrl; + pci_conf = &im->pci_conf; hose = &pci_hose; /* * Release PCI RST Output signal */ - pci_ctrl->gcr = 0; + out_be32(&pci_ctrl->gcr, 0); udelay(2000); - pci_ctrl->gcr = 1; + out_be32(&pci_ctrl->gcr, 1); /* We need to wait at least a 1sec based on PCI specs */ for (i = 0; i < 1000; i++) @@ -84,30 +91,39 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR); + out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M); - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; + out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR); + out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M); /* * Configure PCI Outbound Translation Windows */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M; + out_be32(&pci_pot[0].potar, + (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK); + out_be32(&pci_pot[0].pobar, + (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK); + out_be32(&pci_pot[0].pocmr, + POCMR_EN | POCMR_PRE | POCMR_CM_256M); /* PCI IO space */ - pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; + out_be32(&pci_pot[1].potar, + (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK); + out_be32(&pci_pot[1].pobar, + (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK); + out_be32(&pci_pot[1].pocmr, + POCMR_EN | POCMR_IO | POCMR_CM_16M); /* PCI mmio - non-prefetch mem space */ - pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; + out_be32(&pci_pot[2].potar, + (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK); + out_be32(&pci_pot[2].pobar, + (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK); + out_be32(&pci_pot[2].pocmr, + POCMR_EN | POCMR_CM_256M); /* * Configure PCI Inbound Translation Windows @@ -115,11 +131,12 @@ pci_init_board(void) /* we need RAM mapped to PCI space for the devices to * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + out_be32(&pci_ctrl[0].pitar1, 0x0); + out_be32(&pci_ctrl[0].pibar1, 0x0); + out_be32(&pci_ctrl[0].piebar1, 0x0); + out_be32(&pci_ctrl[0].piwar1, + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1)); hose->first_busno = 0; hose->last_busno = 0xff; diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 7db87a8..16ce770 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 - 2007 + * (C) Copyright 2000 - 2009 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -30,6 +30,8 @@ */ #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -40,21 +42,21 @@ static void fifo_init (volatile psc512x_t *psc) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; /* reset Rx & Tx fifo slice */ - psc->rfcmd = PSC_FIFO_RESET_SLICE; - psc->tfcmd = PSC_FIFO_RESET_SLICE; + out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE); + out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE); /* disable Tx & Rx FIFO interrupts */ - psc->rfintmask = 0; - psc->tfintmask = 0; + out_be32(&psc->rfintmask, 0); + out_be32(&psc->tfintmask, 0); - psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16); - psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16); + out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16)); + out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16)); /* enable Tx & Rx FIFO slice */ - psc->rfcmd = PSC_FIFO_ENABLE_SLICE; - psc->tfcmd = PSC_FIFO_ENABLE_SLICE; + out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE); + out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE); - im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE; + out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE); __asm__ volatile ("sync"); } @@ -68,38 +70,38 @@ int serial_init(void) fifo_init (psc); /* set MR register to point to MR1 */ - psc->command = PSC_SEL_MODE_REG_1; + out_8(&psc->command, PSC_SEL_MODE_REG_1); /* disable Tx/Rx */ - psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; + out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE); /* choose the prescaler by 16 for the Tx/Rx clock generation */ - psc->psc_clock_select = 0xdd00; + out_be16(&psc->psc_clock_select, 0xdd00); /* switch to UART mode */ - psc->sicr = 0; + out_be32(&psc->sicr, 0); /* mode register points to mr1 */ /* configure parity, bit length and so on in mode register 1*/ - psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); /* now, mode register points to mr2 */ - psc->mode = PSC_MODE_1_STOPBIT; + out_8(&psc->mode, PSC_MODE_1_STOPBIT); /* calculate dividor for setting PSC CTUR and CTLR registers */ baseclk = (gd->ips_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xff; + out_8(&psc->ctur, (div >> 8) & 0xff); /* set baudrate */ - psc->ctlr = div & 0xff; + out_8(&psc->ctlr, div & 0xff); /* disable all interrupts */ - psc->psc_imr = 0; + out_be16(&psc->psc_imr, 0); /* reset and enable Rx/Tx */ - psc->command = PSC_RST_RX; - psc->command = PSC_RST_TX; - psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + out_8(&psc->command, PSC_RST_RX); + out_8(&psc->command, PSC_RST_TX); + out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE); return 0; } @@ -113,7 +115,7 @@ void serial_putc (const char c) serial_putc ('\r'); /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) + while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP)) ; psc->tfdata_8 = c; @@ -125,7 +127,7 @@ void serial_putc_raw (const char c) volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) + while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP)) ; psc->tfdata_8 = c; @@ -145,7 +147,7 @@ int serial_getc (void) volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; /* Wait for a character to arrive. */ - while (psc->rfstat & PSC_FIFO_EMPTY) + while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY) ; return psc->rfdata_8; @@ -156,7 +158,7 @@ int serial_tstc (void) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; - return !(psc->rfstat & PSC_FIFO_EMPTY); + return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY); } void serial_setbrg (void) @@ -168,8 +170,8 @@ void serial_setbrg (void) baseclk = (gd->csb_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xFF; - psc->ctlr = div & 0xff; /* set baudrate */ + out_8(&psc->ctur, (div >> 8) & 0xFF); + out_8(&psc->ctlr, div & 0xff); /* set baudrate */ } void serial_setrts(int s) @@ -179,11 +181,11 @@ void serial_setrts(int s) if (s) { /* Assert RTS (become LOW) */ - psc->op1 = 0x1; + out_8(&psc->op1, 0x1); } else { /* Negate RTS (become HIGH) */ - psc->op0 = 0x1; + out_8(&psc->op0, 0x1); } } @@ -192,6 +194,6 @@ int serial_getcts(void) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; - return (psc->ip & 0x1) ? 0 : 1; + return (in_8(&psc->ip) & 0x1) ? 0 : 1; } #endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 1f90862..0fec004 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2007 + * (C) Copyright 2000-2009 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. @@ -28,6 +28,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -75,29 +76,37 @@ int get_clocks (void) u32 csb_clk; u32 ips_clk; u32 pci_clk; + u32 reg; - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + reg = in_be32(&im->sysconf.immrbar); + if ((reg & IMMRBAR_BASE_ADDR) != (u32) im) return -1; - spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + reg = in_be32(&im->clk.spmr); + spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT; spll = ref_clk * spmf_mult[spmf]; - sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; + reg = in_be32(&im->clk.scfr[1]); + sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; csb_clk = sys_clk / 2; - cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + reg = in_be32(&im->clk.spmr); + cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT; core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; - ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; + reg = in_be32(&im->clk.scfr[0]); + ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; if (ips_div != 0) { ips_clk = csb_clk / ips_div; } else { /* in case we cannot get a sane IPS divisor, fail gracefully */ ips_clk = 0; } - pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; + + reg = in_be32(&im->clk.scfr[0]); + pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; if (pci_div != 0) { pci_clk = csb_clk / pci_div; } else { -- cgit v1.1 From 3b74e7ec58e2cc352b0a396a614065cfeb8d138f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 May 2009 10:47:45 +0200 Subject: MPC512x: remove include/mpc512x.h Move needed definitions (register descriptions etc.) from include/mpc512x.h into include/asm-ppc/immap_512x.h. Instead of using a #define'd register offset, use a function that provides the PATA controller's base address. All the rest of include/mpc512x.h are register offset definitions which can be eliminated by proper use of C structures. There are only a few register offsets remaining that are needed in cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h which is intended as a temporary workaround only. In a later patch this file will be removed, too, and then auto-generated from the respective C structs. Signed-off-by: Wolfgang Denk Cc: John Rigby --- cpu/mpc512x/asm-offsets.h | 15 +++++++++++++++ cpu/mpc512x/cpu.c | 1 - cpu/mpc512x/cpu_init.c | 1 - cpu/mpc512x/i2c.c | 1 - cpu/mpc512x/speed.c | 1 - cpu/mpc512x/start.S | 6 ++++-- 6 files changed, 19 insertions(+), 6 deletions(-) create mode 100644 cpu/mpc512x/asm-offsets.h (limited to 'cpu') diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h new file mode 100644 index 0000000..4b14778 --- /dev/null +++ b/cpu/mpc512x/asm-offsets.h @@ -0,0 +1,15 @@ +/* + * needed for cpu/mpc512x/start.S + * + * These should be auto-generated + */ +#define LPCS0AW 0x0024 +#define SRAMBAR 0x00C4 +#define SWCRR 0x0904 +#define LPC_OFFSET 0x10000 +#define CS0_CONFIG 0x00000 +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ + +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 8021bc1..42ccd81 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c index 69ec871..fe6beaf 100644 --- a/cpu/mpc512x/cpu_init.c +++ b/cpu/mpc512x/cpu_init.c @@ -25,7 +25,6 @@ */ #include -#include #include #include diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 4a3f9a0..97bda0d 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_HARD_I2C -#include #include /* by default set I2C bus 0 active */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 0fec004..ce8d094 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -26,7 +26,6 @@ */ #include -#include #include #include #include diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682d..178e5d1 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -1,7 +1,7 @@ /* * Copyright (C) 1998 Dan Malek * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk + * Copyright (C) 2000-2009 Wolfgang Denk * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. * * See file CREDITS for list of people who contributed to this @@ -30,12 +30,14 @@ */ #include -#include #include #include #define CONFIG_521X 1 /* needed for Linux kernel header files*/ +#include +#include "asm-offsets.h" + #include #include -- cgit v1.1 From b8c1d6a54ff8195488b68e163de8ec31f1603496 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Jun 2009 16:53:15 +0200 Subject: mpc512x: Fix PSC divisor calculation for baudrate setting The wrong input frequency was used in serial_setbrg(). This patch fixes this by using ips_clk as input frequency for the PSC baudrate generator. Signed-off-by: Stefan Roese --- cpu/mpc512x/serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 16ce770..d3ffff9 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -167,7 +167,7 @@ void serial_setbrg (void) volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; unsigned long baseclk, div; - baseclk = (gd->csb_clk + 8) / 16; + baseclk = (gd->ips_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; out_8(&psc->ctur, (div >> 8) & 0xFF); -- cgit v1.1 From ba4feae90ca71de1681d5808f17e73224d8f03c4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Jun 2009 16:53:16 +0200 Subject: mpc512x: Use serial_setbrg() in serial_init() to not duplicate the code This patch removes the duplicated code for baudrate generator configuration in the PSC serial_init() implementation by calling serial_setbrg() instead of duplicating the code. Signed-off-by: Stefan Roese --- cpu/mpc512x/serial.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index d3ffff9..4fc4693 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -60,12 +60,24 @@ static void fifo_init (volatile psc512x_t *psc) __asm__ volatile ("sync"); } +void serial_setbrg(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk, div; + + /* calculate dividor for setting PSC CTUR and CTLR registers */ + baseclk = (gd->ips_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + out_8(&psc->ctur, (div >> 8) & 0xff); + out_8(&psc->ctlr, div & 0xff); /* set baudrate */ +} + int serial_init(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; - unsigned long baseclk; - int div; fifo_init (psc); @@ -87,13 +99,8 @@ int serial_init(void) /* now, mode register points to mr2 */ out_8(&psc->mode, PSC_MODE_1_STOPBIT); - /* calculate dividor for setting PSC CTUR and CTLR registers */ - baseclk = (gd->ips_clk + 8) / 16; - div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; - - out_8(&psc->ctur, (div >> 8) & 0xff); /* set baudrate */ - out_8(&psc->ctlr, div & 0xff); + serial_setbrg(); /* disable all interrupts */ out_be16(&psc->psc_imr, 0); @@ -161,19 +168,6 @@ int serial_tstc (void) return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY); } -void serial_setbrg (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; - unsigned long baseclk, div; - - baseclk = (gd->ips_clk + 8) / 16; - div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; - - out_8(&psc->ctur, (div >> 8) & 0xFF); - out_8(&psc->ctlr, div & 0xff); /* set baudrate */ -} - void serial_setrts(int s) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; -- cgit v1.1 From 0f898604945af4543c1525fc33b6bae621a3b805 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 22 May 2009 17:23:24 -0500 Subject: 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser Signed-off-by: Kim Phillips --- cpu/mpc83xx/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index 2f0f1ce..d619426 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -22,7 +22,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ -ffixed-r2 -msoft-float # Use default linker script. Board port can override in board/*/config.mk -- cgit v1.1 From 2c7920afaf96d9779304202cd8a355b4f7576a83 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 22 May 2009 17:23:25 -0500 Subject: 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]x Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 2 +- cpu/mpc83xx/speed.c | 66 +++++++++++++++++++++++++------------------------- 2 files changed, 34 insertions(+), 34 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 8e9c875..d9b96b5 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -185,7 +185,7 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH; #else diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 95b558f..bde7e92 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -100,23 +100,23 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; #endif -#ifdef CONFIG_MPC834X +#ifdef CONFIG_MPC834x u32 usbmph_clk; #endif u32 core_clk; u32 i2c1_clk; -#if !defined(CONFIG_MPC832X) +#if !defined(CONFIG_MPC832x) u32 i2c2_clk; #endif #if defined(CONFIG_MPC8315) u32 tdm_clk; #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) u32 sdhc_clk; #endif u32 enc_clk; @@ -126,17 +126,17 @@ int get_clocks(void) #if defined(CONFIG_MPC8360) u32 mem_sec_clk; #endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) u32 qepmf; u32 qepdf; u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) u32 sata_clk; #endif @@ -164,7 +164,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -202,7 +202,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -229,7 +229,7 @@ int get_clocks(void) tsec2_clk = 0; #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -274,7 +274,7 @@ int get_clocks(void) return -7; } -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { case 0: sdhc_clk = 0; @@ -313,22 +313,22 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; -#elif defined(CONFIG_MPC832X) +#elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC831X) +#elif defined(CONFIG_MPC831x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC837x) i2c1_clk = sdhc_clk; #endif -#if !defined(CONFIG_MPC832X) +#if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -366,7 +366,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -436,7 +436,7 @@ int get_clocks(void) return -13; } -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); @@ -444,23 +444,23 @@ int get_clocks(void) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbdr_clk = usbdr_clk; #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) gd->usbmph_clk = usbmph_clk; #endif #if defined(CONFIG_MPC8315) gd->tdm_clk = tdm_clk; #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) gd->sdhc_clk = sdhc_clk; #endif gd->core_clk = core_clk; gd->i2c1_clk = i2c1_clk; -#if !defined(CONFIG_MPC832X) +#if !defined(CONFIG_MPC832x) gd->i2c2_clk = i2c2_clk; #endif gd->enc_clk = enc_clk; @@ -470,15 +470,15 @@ int get_clocks(void) #if defined(CONFIG_MPC8360) gd->mem_sec_clk = mem_sec_clk; #endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) gd->pciexp1_clk = pciexp1_clk; gd->pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) gd->sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -504,7 +504,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("Clock configuration:\n"); printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); #endif @@ -516,28 +516,28 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); -#if !defined(CONFIG_MPC832X) +#if !defined(CONFIG_MPC832x) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); #endif #if defined(CONFIG_MPC8315) printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk)); #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); #endif -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); #endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk)); #endif return 0; -- cgit v1.1 From 4ef01010aa4799c759d75e67007fdd3a38c88c8a Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Mon, 25 May 2009 17:23:16 +0530 Subject: mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan Signed-off-by: Remy Bohmer --- cpu/mpc83xx/cpu_init.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index d9b96b5..414565c 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,6 +23,10 @@ #include #include #include +#ifdef CONFIG_USB_EHCI_FSL +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif +#ifdef CONFIG_USB_EHCI_FSL + uint32_t temp; + struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; + + /* Configure interface. */ + setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); + + /* Wait for clock to stabilize */ + do { + temp = in_be32((void *)ehci->control); + udelay(1000); + } while (!(temp & PHY_CLK_VALID)); +#endif } int cpu_init_r (void) -- cgit v1.1 From c60dc8527dbb2a1318c03bc18bdebcfbd0164551 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 8 Jun 2009 09:38:07 +0200 Subject: mpc512x: Fix problem with I2C access before relocation This is needed for the upcoming esd MECP5123 board port which uses I2C EEPROM for environment storage. Signed-off-by: Stefan Roese Cc: Reinhard Arlt Acked-by: Heiko Schocher --- cpu/mpc512x/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 97bda0d..e2d9097 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; #include /* by default set I2C bus 0 active */ -static unsigned int bus_num = 0; +static unsigned int bus_num __attribute__ ((section (".data"))) = 0; #define I2C_TIMEOUT 100 #define I2C_RETRIES 3 -- cgit v1.1 From 22419d77976bbd0df9fcf45513f1b96bd73e50d1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 21 May 2009 08:36:43 -0500 Subject: 85xx: Always attempt ethernet device tree fixup Its reasonable that we may have ethernet devices but dont have drivers or support enabled for them in u-boot and want the device tree fixed up. Unconditionally calling the ethernet fixup is fine since if we dont have ethernet nodes that match (or aliases) we will not attempt to do anything. Signed-off-by: Kumar Gala Acked-by: Timur Tabi --- cpu/mpc85xx/fdt.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 26a8f48..a692529 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -278,12 +278,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) if (!IS_E_PROCESSOR(get_svr())) fdt_fixup_crypto_node(blob, 0); -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob); fdt_add_enet_stashing(blob); -#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 8, 1); -- cgit v1.1 From 71b358cc26792889bbac35054d8e89d59b3fabc4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 20 May 2009 01:11:33 -0500 Subject: 85xx: Added MPC8535/E identifiers Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index ef976a4..1c3eddf 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8533, 8533), CPU_TYPE_ENTRY(8533, 8533_E), + CPU_TYPE_ENTRY(8535, 8535), + CPU_TYPE_ENTRY(8535, 8535_E), CPU_TYPE_ENTRY(8536, 8536), CPU_TYPE_ENTRY(8536, 8536_E), CPU_TYPE_ENTRY(8540, 8540), -- cgit v1.1 From b3d7f20f43a0f8d11c65e2f92153b5512b11580c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 20 May 2009 12:30:29 -0400 Subject: 85xx: Add QE clk support Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/speed.c | 15 ++++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 1c3eddf..8f94bad 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -186,6 +186,10 @@ int checkcpu (void) printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif +#ifdef CONFIG_QE + printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index b0f47e0..286b6b2 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo) uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; +#ifdef CONFIG_QE + u32 qe_ratio; +#endif plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif +#ifdef CONFIG_QE + qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) + >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; +#endif + #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -112,6 +121,10 @@ int get_clocks (void) gd->mem_clk = sys_info.freqDDRBus; gd->lbc_clk = sys_info.freqLocalBus; +#ifdef CONFIG_QE + gd->qe_clk = sys_info.freqQE; + gd->brg_clk = gd->qe_clk / 2; +#endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, * there is no pattern that can be used to determine the frequency, so -- cgit v1.1 From 8e55258f144764de8902e9f078a7ad4c6c022c2f Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 4 Jun 2009 16:12:41 -0400 Subject: qe: Pass in uec_info struct through uec_initialize The uec driver contains code to hard code configuration information for the uec ethernet controllers. This patch creates an array of uec_info structures, which are then parsed by the corresponding driver instance to determine configuration. It also creates function uec_standard_init() to initialize all UEC interfaces for 83xx and 85xx. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- cpu/mpc83xx/cpu.c | 20 +++----------------- cpu/mpc85xx/cpu.c | 21 ++++----------------- 2 files changed, 7 insertions(+), 34 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 876f5c7..c4331ae 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -367,24 +367,10 @@ int dma_xfer(void *dest, u32 count, void *src) */ int cpu_eth_init(bd_t *bis) { -#if defined(CONFIG_UEC_ETH1) - uec_initialize(0); -#endif -#if defined(CONFIG_UEC_ETH2) - uec_initialize(1); -#endif -#if defined(CONFIG_UEC_ETH3) - uec_initialize(2); -#endif -#if defined(CONFIG_UEC_ETH4) - uec_initialize(3); -#endif -#if defined(CONFIG_UEC_ETH5) - uec_initialize(4); -#endif -#if defined(CONFIG_UEC_ETH6) - uec_initialize(5); +#if defined(CONFIG_UEC_ETH) + uec_standard_init(bis); #endif + #if defined(CONFIG_TSEC_ENET) tsec_standard_init(bis); #endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 8f94bad..9ad1188 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -383,24 +383,11 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); #endif -#if defined(CONFIG_UEC_ETH1) - uec_initialize(0); -#endif -#if defined(CONFIG_UEC_ETH2) - uec_initialize(1); -#endif -#if defined(CONFIG_UEC_ETH3) - uec_initialize(2); -#endif -#if defined(CONFIG_UEC_ETH4) - uec_initialize(3); -#endif -#if defined(CONFIG_UEC_ETH5) - uec_initialize(4); -#endif -#if defined(CONFIG_UEC_ETH6) - uec_initialize(5); + +#if defined(CONFIG_UEC_ETH) + uec_standard_init(bis); #endif + #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) tsec_standard_init(bis); #endif -- cgit v1.1 From b1f12650d332eadac1306a772cab6096abee6ddd Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Thu, 21 May 2009 12:09:59 -0500 Subject: fsl: Create common fsl_dma.h for 85xx and 86xx cpus Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 31 +++++++++++++++++-------------- cpu/mpc86xx/cpu.c | 27 +++++++++++++++------------ 2 files changed, 32 insertions(+), 26 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9ad1188..331fcc0 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -266,26 +266,28 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); + volatile fsl_dma_t *dma = &dma_base->dma[0]; - dma->satr0 = 0x02c40000; - dma->datr0 = 0x02c40000; - dma->sr0 = 0xfffffff; /* clear any errors */ + dma->satr = 0x02c40000; + dma->datr = 0x02c40000; + dma->sr = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); - volatile uint status = dma->sr0; + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); + volatile fsl_dma_t *dma = &dma_base->dma[0]; + volatile uint status = dma->sr; /* While the channel is busy, spin */ while((status & 4) == 4) { - status = dma->sr0; + status = dma->sr; } /* clear MR0[CS] channel start bit */ - dma->mr0 &= 0x00000001; + dma->mr &= 0x00000001; asm("sync;isync;msync"); if (status != 0) { @@ -295,14 +297,15 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); + volatile fsl_dma_t *dma = &dma_base->dma[0]; - dma->dar0 = (uint) dest; - dma->sar0 = (uint) src; - dma->bcr0 = count; - dma->mr0 = 0xf000004; + dma->dar = (uint) dest; + dma->sar = (uint) src; + dma->bcr = count; + dma->mr = 0xf000004; asm("sync;isync;msync"); - dma->mr0 = 0xf000005; + dma->mr = 0xf000005; asm("sync;isync;msync"); return dma_check(); } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 653a137..f35323a 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -183,10 +183,11 @@ void dma_init(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile fsl_dma_t *dma = &dma_base->dma[0]; - dma->satr0 = 0x00040000; - dma->datr0 = 0x00040000; + dma->satr = 0x00040000; + dma->datr = 0x00040000; asm("sync; isync"); } @@ -194,12 +195,13 @@ uint dma_check(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; - volatile uint status = dma->sr0; + volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile fsl_dma_t *dma = &dma_base->dma[0]; + volatile uint status = dma->sr; /* While the channel is busy, spin */ while ((status & 4) == 4) { - status = dma->sr0; + status = dma->sr; } if (status != 0) { @@ -212,14 +214,15 @@ int dma_xfer(void *dest, uint count, void *src) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile fsl_dma_t *dma = &dma_base->dma[0]; - dma->dar0 = (uint) dest; - dma->sar0 = (uint) src; - dma->bcr0 = count; - dma->mr0 = 0xf000004; + dma->dar = (uint) dest; + dma->sar = (uint) src; + dma->bcr = count; + dma->mr = 0xf000004; asm("sync;isync"); - dma->mr0 = 0xf000005; + dma->mr = 0xf000005; asm("sync;isync"); return dma_check(); } -- cgit v1.1 From 2f21ce4d546d31289ac49a680f78bcc9a792c6ec Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Thu, 21 May 2009 12:10:00 -0500 Subject: fsl/85xx, 86xx: Sync up DMA code The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 8 ++++---- cpu/mpc86xx/cpu.c | 14 ++++++++------ 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 331fcc0..d88c564 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -269,9 +269,9 @@ void dma_init(void) { volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); volatile fsl_dma_t *dma = &dma_base->dma[0]; - dma->satr = 0x02c40000; - dma->datr = 0x02c40000; - dma->sr = 0xfffffff; /* clear any errors */ + dma->satr = 0x00040000; + dma->datr = 0x00040000; + dma->sr = 0xffffffff; /* clear any errors */ asm("sync; isync; msync"); return; } @@ -286,7 +286,7 @@ uint dma_check(void) { status = dma->sr; } - /* clear MR0[CS] channel start bit */ + /* clear MR[CS] channel start bit */ dma->mr &= 0x00000001; asm("sync;isync;msync"); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index f35323a..d47cc5e 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -182,20 +182,19 @@ watchdog_reset(void) void dma_init(void) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); volatile fsl_dma_t *dma = &dma_base->dma[0]; dma->satr = 0x00040000; dma->datr = 0x00040000; + dma->sr = 0xffffffff; /* clear any errors */ asm("sync; isync"); } uint dma_check(void) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); volatile fsl_dma_t *dma = &dma_base->dma[0]; volatile uint status = dma->sr; @@ -204,6 +203,10 @@ dma_check(void) status = dma->sr; } + /* clear MR[CS] channel start bit */ + dma->mr &= 0x00000001; + asm("sync;isync"); + if (status != 0) { printf("DMA Error: status = %x\n", status); } @@ -213,8 +216,7 @@ dma_check(void) int dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_dma_t *dma_base = &immap->im_dma; + volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); volatile fsl_dma_t *dma = &dma_base->dma[0]; dma->dar = (uint) dest; -- cgit v1.1