This is the first commit for the u-boot zylonite port. The following has be

done so far:

	* created zylonite board dir (based on lubbock)
	* extended some - but not all pxa sources and headers for Intel
	  Monahans support (CONFIG_CPU_MONAHANS)
	* created Makefile zylonite target + MAKEALL entry
	* added some debug nonsense, remove later, grep for mk@tbd

Status: compiles (eldk-4.0), and can be started with BDI, but runs forever
	and doesn't halt at breakpoints. Hmmm...

3 files changed, 47 insertions, 12 deletions

diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index d1551dd..445ba18 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -143,6 +143,7 @@ int dcache_status (void)
 	return 0;					/* always off */
 }
 
+#ifndef CONFIG_CPU_MONAHANS
 void set_GPIO_mode(int gpio_mode)
 {
 	int gpio = gpio_mode & GPIO_MD_MASK_NR;
@@ -160,3 +161,5 @@ void set_GPIO_mode(int gpio_mode)
 	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
 	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 }
+#endif /* CONFIG_CPU_MONAHANS */
+
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index cedebfe..9bf2a7c 100644
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -54,7 +54,11 @@ void serial_setbrg (void)
 		hang ();
 
 #ifdef CONFIG_FFUART
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_22_FFUART;
+#else
 	CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
 	FFIER = 0;					/* Disable for now */
 	FFFCR = 0;					/* No fifos enabled */
@@ -68,7 +72,11 @@ void serial_setbrg (void)
 	FFIER = IER_UUE;			/* Enable FFUART */
 
 #elif defined(CONFIG_BTUART)
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_21_BTUART;
+#else
 	CKEN |= CKEN7_BTUART;
+#endif /*  CONFIG_CPU_MONAHANS */
 
 	BTIER = 0;
 	BTFCR = 0;
@@ -82,7 +90,11 @@ void serial_setbrg (void)
 	BTIER = IER_UUE;			/* Enable BFUART */
 
 #elif defined(CONFIG_STUART)
+#ifdef CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_23_STUART;
+#else
 	CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
 	STIER = 0;
 	STFCR = 0;
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index a8cc080..9940826 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -190,10 +190,10 @@ cpuspeed:	.word	CFG_CPUSPEED
 #endif
 
 
-	/* RS: ???							    */
-	.macro CPWAIT
-	mrc  p15,0,r0,c2,c0,0
-	mov  r0,r0
+	/* takes care the CP15 update has taken place */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
 	sub  pc,pc,#4
 	.endm
 
@@ -201,13 +201,28 @@ cpuspeed:	.word	CFG_CPUSPEED
 cpu_init_crit:
 
 	/* mask all IRQs						    */
+#ifndef CONFIG_CPU_MONAHANS
+	
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]
+#else
+	/* Step 1 - Enable CP6 permission */
+        mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
+        orr     r1, r1, #0x40
+	        mcr     p15, 0, r1, c15, c1, 0
+        CPWAIT  r1
+
+        /* Step 2 - Mask ICMR & ICMR2 */
+        mov     r1, #0
+        mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+	mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
+#endif
 
-#if defined(CFG_CPUSPEED)
-
-	/* set clock speed */
+#ifndef CONFIG_CPU_MONAHANS
+#ifdef CFG_CPUSPEED
+	
+	/* set clock speed tbd@mk: required for monahans? */
 	ldr	r0, CC_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #CCCR]
@@ -215,7 +230,10 @@ cpu_init_crit:
 	mcr	p14, 0, r0, c6, c0, 0
 
 setspeed_done:
-#endif
+	
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
+	
 
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -227,19 +245,21 @@ setspeed_done:
 	mov	lr,	ip
 
 	/* Memory interfaces are working. Disable MMU and enable I-cache.   */
+	/* mk: hmm, this is not in the monahans docs, leave it now but 
+	 *     check here if it doesn't work :-) */
 
 	ldr	r0, =0x2001		/* enable access to all coproc.	    */
 	mcr	p15, 0, r0, c15, c1, 0
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write & fill buffers   */
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c7, c7, 0	/* flush Icache, Dcache and BTB	    */
-	CPWAIT
+	CPWAIT r0
 
 	mcr	p15, 0, r0, c8, c7, 0	/* flush instuction and data TLBs   */
-	CPWAIT
+	CPWAIT r0
 
 	/* Enable the Icache						    */
 /*