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authorStefan Roese <sr@denx.de>2008-07-01 17:03:19 +0200
committerStefan Roese <sr@denx.de>2008-07-01 17:03:19 +0200
commitdd1c5523d6f44e842e69f2fcb50788c6060eab86 (patch)
treed20aa28e6c3eb4d7b9303366306ad51fc36fa89e /cpu/ppc4xx
parent745d8a0d3cea82e6d1753e14afb4588c34761b15 (diff)
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ppc4xx: Fix 460EX/GT PCIe port initialization
This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r--cpu/ppc4xx/4xx_pcie.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 503facc..d50a538 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -615,22 +615,20 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
- u32 val = 1 << 24;
+ u32 val;
u32 utlset1;
- if (rootport) {
+ if (rootport)
val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- } else {
+ else
val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- }
if (port == 0) {
val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
} else {
val |= LNKW_X4 << 12;
- utlset1 |= 0x00101101;
+ utlset1 = 0x20101101;
}
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);