Merge with /home/stefan/git/u-boot/denx

5 files changed, 70 insertions, 34 deletions

diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 16dc8d6..baecf70 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -41,7 +41,7 @@ START	:= $(addprefix $(obj),$(START))
 all:	$(obj).depend $(START) $(LIB)
 
 $(LIB):	$(OBJS)
-	$(AR) crv $@ $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 #########################################################################
 
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 4e81ce2..faa5257 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -196,6 +196,7 @@ int checkcpu (void)
 	char buf[32];
 
 #if !defined(CONFIG_IOP480)
+	char addstr[64] = "";
 	sys_info_t sys_info;
 
 	puts ("CPU:   ");
@@ -312,19 +313,23 @@ int checkcpu (void)
 #endif /* CONFIG_440 */
 
 	case PVR_440EPX1_RA:
-		puts("EPx Rev. A - Security/Kasumi support");
+		puts("EPx Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_440EPX2_RA:
-		puts("EPx Rev. A - No Security/Kasumi support");
+		puts("EPx Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
 		break;
 
 	case PVR_440GRX1_RA:
-		puts("GRx Rev. A - Security/Kasumi support");
+		puts("GRx Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_440GRX2_RA:
-		puts("GRx Rev. A - No Security/Kasumi support");
+		puts("GRx Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
 		break;
 
 	case PVR_440SP_RA:
@@ -353,13 +358,16 @@ int checkcpu (void)
 	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
 	       FREQ_EBC / 1000000);
 
+	if (addstr[0] != 0)
+		printf("       %s\n", addstr);
+
 #if defined(I2C_BOOTROM)
 	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 #if defined(SDR0_PINSTP_SHIFT)
 	printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
 	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
-#endif
-#endif
+#endif	/* SDR0_PINSTP_SHIFT */
+#endif	/* I2C_BOOTROM */
 
 #if defined(CONFIG_PCI)
 	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index b27567f..def46f1 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -226,13 +226,19 @@ cpu_init_f (void)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);   /* output select */
+#if defined(CFG_GPIO0_OR)
+	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
+#endif
+#if defined(CFG_GPIO0_ODR)
+	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
+#endif
+	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
 	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
 	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);   /* three-state select */
+	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
 	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-	out32(GPIO0_TCR, CFG_GPIO0_TCR);     /* enable output driver for outputs */
+	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
 
 	/*
 	 * Set EMAC noise filter bits
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index c255f93..3521731 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -65,8 +65,8 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
 
 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 
 	if (hwctl & 0x1)
 		out8(base + NDFC_CMD, byte);
@@ -78,16 +78,16 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
 
 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 
 	return (in8(base + NDFC_DATA));
 }
 
 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 
 	while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
 		;
@@ -110,31 +110,31 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  */
 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 	uint32_t *p = (uint32_t *) buf;
 
-	for(;len > 0; len -= 4)
+	for (;len > 0; len -= 4)
 		*p++ = in32(base + NDFC_DATA);
 }
 
 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 	uint32_t *p = (uint32_t *) buf;
 
-	for(; len > 0; len -= 4)
+	for (; len > 0; len -= 4)
 		out32(base + NDFC_DATA, *p++);
 }
 
 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-        struct nand_chip *this = mtdinfo->priv;
-        ulong base = (ulong) this->IO_ADDR_W;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 	uint32_t *p = (uint32_t *) buf;
 
-	for(; len > 0; len -= 4)
+	for (; len > 0; len -= 4)
 		if (*p++ != in32(base + NDFC_DATA))
 			return -1;
 
@@ -142,8 +142,25 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 }
 #endif /* #ifndef CONFIG_NAND_SPL */
 
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	/*
+	 * Don't use "chip" to address the NAND device,
+	 * generate the cs from the address where it is encoded.
+	 */
+	int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+	ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
+	/* Set NandFlash Core Configuration Register */
+	/* 1col x 2 rows */
+	out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
+}
+
 void board_nand_init(struct nand_chip *nand)
 {
+	int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+	ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
 	nand->eccmode = NAND_ECC_SOFT;
 
 	nand->hwcontrol  = ndfc_hwcontrol;
@@ -166,10 +183,11 @@ void board_nand_init(struct nand_chip *nand)
 	mtebc(pb0ap, CFG_EBC_PB0AP);
 #endif
 
-	/* Set NandFlash Core Configuration Register */
-	/* Chip select 3, 1col x 2 rows */
-	out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
-	out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);
+	/*
+	 * Select required NAND chip in NDFC
+	 */
+	board_nand_select_device(nand, cs);
+	out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
 }
 
 #endif
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 5a1ab38..3fe13da 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -173,9 +173,9 @@
 
 /**************************************************************************/
 _start_440:
-        /*--------------------------------------------------------------------+
-        | 440EPX BUP Change - Hardware team request
-        +--------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------+
+	| 440EPX BUP Change - Hardware team request
+	+--------------------------------------------------------------------*/
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	sync
 	nop
@@ -1697,7 +1697,8 @@ ppc405ep_init:
 	mtdcr	ebccfgd,r3
 #endif
 
-	addi	r3,0,CPC0_PCI_HOST_CFG_EN
+#ifndef CFG_CPC0_PCI
+	li	r3,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA
 	/*
 	!-----------------------------------------------------------------------
@@ -1712,6 +1713,9 @@ ppc405ep_init:
 	beq	..pci_cfg_set		  /* if not set, then bypass reg write*/
 #endif
 	ori	r3,r3,CPC0_PCI_ARBIT_EN
+#else /* CFG_CPC0_PCI */
+	li	r3,CFG_CPC0_PCI
+#endif /* CFG_CPC0_PCI */
 ..pci_cfg_set:
 	mtdcr	CPC0_PCI, r3		 /* Enable internal arbiter*/