summaryrefslogtreecommitdiff
path: root/cpu/ppc4xx/sdram.c
diff options
context:
space:
mode:
authorMarkus Klotzbuecher <mk@denx.de>2008-07-10 10:26:07 +0200
committerMarkus Klotzbuecher <mk@denx.de>2008-07-10 10:26:07 +0200
commit794a5924972fc8073616e98a2668da4a5f9aea90 (patch)
treedd0db39b3e183b5bcb0300d5377d7a0d5ac5fd0c /cpu/ppc4xx/sdram.c
parentf2aeecc320f5b181b30effcaa67683aec8d5a843 (diff)
parent4188f0491886b3b486164e819c0a83fdb97efd7d (diff)
downloadu-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.zip
u-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.tar.gz
u-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.tar.bz2
Merge branch 'master' of git://www.denx.de/git/u-boot
Diffstat (limited to 'cpu/ppc4xx/sdram.c')
-rw-r--r--cpu/ppc4xx/sdram.c56
1 files changed, 10 insertions, 46 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 2724d91..7d60ad6 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -31,6 +31,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include "sdram.h"
+#include "ecc.h"
#ifdef CONFIG_SDRAM_BANK0
@@ -163,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-void sdram_init(void)
+phys_size_t initdram(int board_type)
{
ulong speed;
ulong sdtr1;
@@ -231,9 +232,15 @@ void sdram_init(void)
mtsdram(mem_mcopt1, 0);
}
#endif
- return;
+
+ /*
+ * OK, size detected -> all done
+ */
+ return mb0cf[i].size;
}
}
+
+ return 0;
}
#else /* CONFIG_440 */
@@ -332,49 +339,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
-#ifdef CONFIG_SDRAM_ECC
-static void ecc_init(ulong start, ulong size)
-{
- ulong current_addr; /* current byte address */
- ulong end_addr; /* end of memory region */
- ulong addr_inc; /* address skip between writes */
- ulong cfg0_reg; /* for restoring ECC state */
-
- /*
- * TODO: Enable dcache before running this test (speedup)
- */
-
- mfsdram(mem_cfg0, cfg0_reg);
- mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN);
-
- /*
- * look at geometry of SDRAM (data width) to determine whether we
- * can skip words when writing
- */
- if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
- addr_inc = 4;
- else
- addr_inc = 8;
-
- current_addr = start;
- end_addr = start + size;
-
- while (current_addr < end_addr) {
- *((ulong *)current_addr) = 0x00000000;
- current_addr += addr_inc;
- }
-
- /*
- * TODO: Flush dcache and disable it again
- */
-
- /*
- * Enable ecc checking and parity errors
- */
- mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK);
-}
-#endif
-
/*
* Autodetect onboard DDR SDRAM on 440 platforms
*
@@ -382,7 +346,7 @@ static void ecc_init(ulong start, ulong size)
* so this should be extended for other future boards
* using this routine!
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
int i;
int tr1_bank1;