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authorStefan Roese <sr@denx.de>2007-08-14 14:44:41 +0200
committerStefan Roese <sr@denx.de>2007-08-14 14:44:41 +0200
commit779e975117a75e91fcebe226a63104dbfb924ab1 (patch)
tree42f48ba97342287f8e155cce29e8e0600064a16f /cpu/ppc4xx/sdram.c
parentc5a172a5fd636c12467429e3f7910e53773979c6 (diff)
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ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/sdram.c')
-rw-r--r--cpu/ppc4xx/sdram.c27
1 files changed, 19 insertions, 8 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 3a0ca17..2724d91 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -187,14 +187,14 @@ void sdram_init(void)
/*
* Disable memory controller.
*/
- mtsdram0(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
- mtsdram0(mem_mb0cf, mb0cf[i].reg);
- mtsdram0(mem_sdtr1, sdtr1);
- mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
+ mtsdram(mem_mb0cf, mb0cf[i].reg);
+ mtsdram(mem_sdtr1, sdtr1);
+ mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@@ -203,7 +203,7 @@ void sdram_init(void)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram0(mem_mcopt1, 0x80800000);
+ mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@@ -215,10 +215,21 @@ void sdram_init(void)
#ifdef CONFIG_SDRAM_BANK1
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
- mtsdram0(mem_mcopt1, 0x00000000);
- mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
- mtsdram0(mem_mcopt1, 0x80800000);
+ mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
+
+ /*
+ * Check if 2nd bank is really available.
+ * If the size not equal to the size of the first
+ * bank, then disable the 2nd bank completely.
+ */
+ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
+ mb0cf[i].size) {
+ mtsdram(mem_mb1cf, 0);
+ mtsdram(mem_mcopt1, 0);
+ }
#endif
return;
}