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authorStefan Roese <sr@denx.de>2007-10-03 14:14:58 +0200
committerStefan Roese <sr@denx.de>2007-10-31 21:20:49 +0100
commit94276eb0a7a35b9e8c053d589ae225b0f017a237 (patch)
tree944b47011aed98c42f83edc8f0d7e3d914404109 /cpu/ppc4xx/4xx_pcie.c
parent03d344bb6a5f082ea10ec9d753558ea7dfd1c626 (diff)
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ppc4xx: Add a comment for 405EX PCIe endpoint configuration
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/4xx_pcie.c')
-rw-r--r--cpu/ppc4xx/4xx_pcie.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 2bc9638..177e2ad 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -431,6 +431,12 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
u32 val;
+ /*
+ * test-only:
+ * This needs some testing and perhaps changes for
+ * endpoint configuration. Probably no PHY reset at all, etc.
+ * sr, 2007-10-03
+ */
if (rootport)
val = 0x00401000;
else