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| author | Stefan Roese <sr@denx.de> | 2006-08-15 14:22:35 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-08-15 14:22:35 +0200 |
| commit | 899620c2d66d4eef3b2a0034d062e71d45d886c9 (patch) | |
| tree | 5e99c4d42663193423bab1bc17308426c171cc56 /cpu/ppc4xx/4xx_enet.c | |
| parent | f0ff4692ff3372dec55074a8eb444943ab095abb (diff) | |
| download | u-boot-imx-899620c2d66d4eef3b2a0034d062e71d45d886c9.zip u-boot-imx-899620c2d66d4eef3b2a0034d062e71d45d886c9.tar.gz u-boot-imx-899620c2d66d4eef3b2a0034d062e71d45d886c9.tar.bz2 | |
Add initial support for the ALPR board from Prodrive
NAND needs some additional testing
Patch by Heiko Schocher, 15 Aug 2006
Diffstat (limited to 'cpu/ppc4xx/4xx_enet.c')
| -rw-r--r-- | cpu/ppc4xx/4xx_enet.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index fab65af..d166993 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -502,6 +502,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { +#if defined(CONFIG_88E1111_CLK_DELAY) + /* + * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs + * the "RGMII transmit timing control" and "RGMII receive + * timing control" bits set, so that Gbit communication works + * without problems. + * Also set the "Transmitter disable" to 1 to enable the + * transmitter. + * After setting these bits a soft-reset must occur for this + * change to become active. + */ + miiphy_read (dev->name, reg, 0x14, ®_short); + reg_short |= (1 << 7) | (1 << 1) | (1 << 0); + miiphy_write (dev->name, reg, 0x14, reg_short); +#endif miiphy_reset (dev->name, reg); #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |