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| author | Dave Liu <daveliu@freescale.com> | 2010-03-05 12:22:00 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-07 00:07:23 -0500 |
| commit | ec145e87b80f6764d17a6b0aebf521fe758c3fdc (patch) | |
| tree | 41e5ea01cfc6d023c4789bdf759f447c7cc43dad /cpu/mpc8xxx/ddr/ctrl_regs.c | |
| parent | ab467c512e79dbd14f02352655f054a4304c457e (diff) | |
| download | u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.zip u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.tar.gz u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.tar.bz2 | |
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..03f9c43 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,9 +1,10 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. */ /* @@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) } /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ @@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ #if defined(CONFIG_FSL_DDR3) - /* We need set BL/2 + 4 for BC4 or OTF */ - rrt = 4; /* BL/2 + 4 clocks */ - wwt = 4; /* BL/2 + 4 clocks */ + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } dll_lock = 1; /* tDLLK = 512 clocks from spec */ #endif ddr->timing_cfg_4 = (0 @@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr); + set_timing_cfg_4(ddr, popts); set_timing_cfg_5(ddr); set_ddr_zq_cntl(ddr, zq_en); |