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authorJon Loeliger <jdl@freescale.com>2006-04-27 10:15:16 -0500
committerJon Loeliger <jdl@freescale.com>2006-04-27 10:15:16 -0500
commit5c9efb36a6b5431423f52888a0e3b4b515fe7eca (patch)
treeb4e456a06357346267f16a636af658cc85bf5b64 /cpu/mpc86xx/spd_sdram.c
parenta2320a6bf8113a09544c42d160d10ac69d049a03 (diff)
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Cleanup whitespaces and style issues.
Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft.
Diffstat (limited to 'cpu/mpc86xx/spd_sdram.c')
-rw-r--r--cpu/mpc86xx/spd_sdram.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 9c07f20..9ce31d7 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -179,7 +179,7 @@ spd_sdram(void)
unsigned int law_size;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
-
+
/*
* Read SPD information.
*/
@@ -614,7 +614,7 @@ spd_sdram(void)
ddr1->timing_cfg_2 = (0
| ((add_lat & 0x7) << 28) /* ADD_LAT */
- | ((cpo & 0x1f) << 23) /* CPO */
+ | ((cpo & 0x1f) << 23) /* CPO */
| ((wr_lat & 0x7) << 19) /* WR_LAT */
| ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
| ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
@@ -806,7 +806,7 @@ spd_sdram(void)
/*
* Memory will be initialized via DMA, or not at all.
*/
- d_init = 0;
+ d_init = 0;
#endif
ddr1->sdram_cfg_2 = (0
@@ -946,8 +946,7 @@ spd_sdram(void)
| (LAWAR_SIZE & law_size));
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
debug("DDR: LARAR1=0x%08x\n", mcm->lawar1);
-
-
+
return memsize * 1024 * 1024;
}