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| author | Andrew Klossner <andrew@cesa.opbu.xerox.com> | 2008-07-02 07:03:53 -0700 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-07-14 18:46:32 -0500 |
| commit | 24ef76f320fbadf074105229826514db140f939f (patch) | |
| tree | b90675309ccbe0b83ebad7532eea452f72c00c74 /cpu/mpc85xx | |
| parent | 06b4186c10204b6683edb047ac5f506fb0ce0937 (diff) | |
| download | u-boot-imx-24ef76f320fbadf074105229826514db140f939f.zip u-boot-imx-24ef76f320fbadf074105229826514db140f939f.tar.gz u-boot-imx-24ef76f320fbadf074105229826514db140f939f.tar.bz2 | |
Change the temp map to ROM to align addresses to page size.
With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB. The hardware silently truncates
them so the code happens to work. This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/start.S | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2b5d90e..10fe936 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -188,11 +188,12 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l - lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + /* Align the mapping to 16MB */ + lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 |