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| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:49 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:38 +0200 |
| commit | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (patch) | |
| tree | 3c4f9b6df2d712f18b25733a4648a14eea291bfe /cpu/mpc85xx | |
| parent | d50c7d4be150b2252c0d2e16cfcf69643bdd6dc9 (diff) | |
| download | u-boot-imx-08ef89ecd174969b3544f3f0c7cd1de3c57f737b.zip u-boot-imx-08ef89ecd174969b3544f3f0c7cd1de3c57f737b.tar.gz u-boot-imx-08ef89ecd174969b3544f3f0c7cd1de3c57f737b.tar.bz2 | |
Use strmhz() to format clock frequencies
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9c4f214..b8f9125 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -83,6 +83,7 @@ int checkcpu (void) uint ver; uint major, minor; struct cpu_type *cpu; + char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) @@ -138,21 +139,24 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); - printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: - printf(" DDR:%4lu MHz (%lu MT/s data rate), ", - DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; default: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; } @@ -175,14 +179,14 @@ int checkcpu (void) */ clkdiv *= 2; #endif - printf("LBC:%4lu MHz\n", - DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); + printf("LBC:%-4s MHz\n", + strmhz(buf1, sysinfo.freqSystemBus / clkdiv)); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } #ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |