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authorWolfgang Denk <wd@denx.de>2010-01-26 22:29:51 +0100
committerWolfgang Denk <wd@denx.de>2010-01-26 22:29:51 +0100
commit0a42c3a433e25dd30b5062aa251f5a240478cbbb (patch)
tree558cc8b14b64c36db3cfd6b666e455ab67149e5d /cpu/mpc85xx
parent5912d3650740468329a0df014109132431d2140d (diff)
parent66e821ebe96123b3a81ec9ca25cec9c0560fe232 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/fdt.c18
-rw-r--r--cpu/mpc85xx/speed.c23
2 files changed, 32 insertions, 9 deletions
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index af0e78e..1d11ab4 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob)
#define ft_fixup_dpaa_clks(x)
#endif
+#ifdef CONFIG_QE
+static void ft_fixup_qe_snum(void *blob)
+{
+ unsigned int svr;
+
+ svr = mfspr(SPRN_SVR);
+ if (SVR_SOC_VER(svr) == SVR_8569_E) {
+ if(IS_SVR_REV(svr, 1, 0))
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "fsl,qe-num-snums", 46, 1);
+ else
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "fsl,qe-num-snums", 76, 1);
+ }
+}
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
@@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"bus-frequency", gd->lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
+ ft_fixup_qe_snum(blob);
#endif
#ifdef CONFIG_SYS_NS16550
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2103e2e..268edbc 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo)
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
- sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+ sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
@@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL)
- sysInfo->freqPME = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqPME = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL)
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL)
- sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
#endif
#endif
@@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+#if defined(CONFIG_FSL_CORENET)
+ /* If this is corenet based SoC, bit-representation
+ * for four times the clock divider values.
+ */
+ lcrr_div *= 4;
+#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
/*
* Yes, the entire PQ38 family use the same