From 93cedc71647b4b72ac9b48e11997eb2f91645001 Mon Sep 17 00:00:00 2001 From: James Yang Date: Tue, 12 Jan 2010 15:50:18 -0600 Subject: ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2103e2e..8dab8d1 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[2] = sysclk; freqCC_PLL[3] = sysclk; - sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; - sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f); freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; -- cgit v1.1 From 693416fe01d324472d270ac28389022eb82c7217 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 25 Jan 2010 11:01:51 -0600 Subject: Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies" This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922. The original code was correct. I clearly need glasses or a brown paper bag. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 8dab8d1..9193992 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = sysInfo->freqSystemBus / 2; - else sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; #endif #endif -- cgit v1.1 From 0fd2fa6cce6eb91271ebf9733878d0f1fcbc9b32 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 17 Nov 2009 20:49:05 +0800 Subject: Fix the local bus divider mapping The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 9193992..268edbc 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ +#if defined(CONFIG_FSL_CORENET) + /* If this is corenet based SoC, bit-representation + * for four times the clock divider values. + */ + lcrr_div *= 4; +#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) /* * Yes, the entire PQ38 family use the same -- cgit v1.1 From 46df64f22c471b010161aa68bfdbfe94ea46e7bd Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 15 Jan 2010 14:58:40 +0800 Subject: qe: fixup the snum for MPC8569 Rev2.0 Since 1.0 and 2.0 use different snum table, we fixup the snum value according to SPRN_SVR. Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index af0e78e..1d11ab4 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob) #define ft_fixup_dpaa_clks(x) #endif +#ifdef CONFIG_QE +static void ft_fixup_qe_snum(void *blob) +{ + unsigned int svr; + + svr = mfspr(SPRN_SVR); + if (SVR_SOC_VER(svr) == SVR_8569_E) { + if(IS_SVR_REV(svr, 1, 0)) + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 46, 1); + else + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 76, 1); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", gd->lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); + ft_fixup_qe_snum(blob); #endif #ifdef CONFIG_SYS_NS16550 -- cgit v1.1