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| author | Stefan Roese <sr@denx.de> | 2007-12-27 19:37:26 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-12-27 19:37:26 +0100 |
| commit | bb701283a8dcb2521000fe437f19a83cadc98b02 (patch) | |
| tree | c8fe6881bf3b607b18b098009a64650357e848f5 /cpu/mpc85xx/spd_sdram.c | |
| parent | b568fd25574181a3b12ae3d66b2913903442cb83 (diff) | |
| parent | 0dcfe3a225a9436fc514f374a19242c672f1172b (diff) | |
| download | u-boot-imx-bb701283a8dcb2521000fe437f19a83cadc98b02.zip u-boot-imx-bb701283a8dcb2521000fe437f19a83cadc98b02.tar.gz u-boot-imx-bb701283a8dcb2521000fe437f19a83cadc98b02.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2
Diffstat (limited to 'cpu/mpc85xx/spd_sdram.c')
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 5dc223a..553f736 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -53,8 +53,8 @@ picos_to_clk(int picos) { int clks; - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks = picos / (2000000000 / (get_ddr_freq(0) / 1000)); + if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) { clks++; } @@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh) long int spd_sdram(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -309,7 +308,7 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } @@ -422,7 +421,7 @@ spd_sdram(void) * Adjust the CAS Latency to allow for bus speeds that * are slower than the DDR module. */ - busfreq = get_bus_freq(0) / 1000000; /* MHz */ + busfreq = get_ddr_freq(0) / 1000000; /* MHz */ effective_data_rate = max_data_rate; if (busfreq < 90) { @@ -1023,8 +1022,7 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); |